11
LatticeECP2M PCI Express x4
Lattice Semiconductor
Evaluation Board User’s Guide
Note: LEDs will illuminate if connected to an unprogrammed FPGA pin. It is recommended that a pull-down be pro-
grammed on FPGA output pins.
17-Segment LED Display
(see Appendix A, Figure 14)
General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins
can be driven low to illuminate the display segments.
Figure 4. 17-Segment LED Display
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit the
evaluation of several types of FPGA I/O buffers. The use of several termination schemes permits an easy interface
for each buffer type.
Table 8. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13)
SMA
Designation
Name
LFE2M35E
Signal
672-BGA
Termination
Description
Termination
Resistor(s)
J37
LVDS_I
N
P0
PR37A
N
23
100-ohm Differential
R130
J39
LVDS_I
NN
0
PR37B
M21
LVDS_I
N
P1
PR41A
P24
100-ohm Differential
R132
LVDS_I
NN
1
PR41B
P23
J45
LVDS_I
N
P2
PR51A
T24
100-ohm Differential
R134
J47
LVDS_I
NN
2
PR51B
U24
J49*
LVDS_I
N
P3
PR57A
V24
100-ohm Differential
R136
J51*
LVDS_I
NN
3
PR57B
W24
J38
LVDS_OUTP0
PR50A
T23
100-ohm Differential
R131
J40
LVDS_OUT
N
0
PR50B
T22
J42
LVDS_OUTP1
PR53A
V26
100-ohm Differential
R133
Se
g
ment
BGA
A
B
C
D
E
F
G
H
K
M
N
P
R
S
T
U
DP
H2
J3
G1
H3
J7
H5
G5
G6
F3
J
8
E1
J9
E3
F5
D3
F6
C2
A
B
C
D
G
F
E
DP
H
T S R
K M N
U
P
