Programming Cables
User Guide
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FPGA-UG-02042-26.2
4.
Programming Software
Diamond Programmer and ispVM System for Classic devices is the preferred programming management software tool
for all Lattice devices and download cables. The latest version of Lattice Diamond Programmer or ispVM System
software is available for download from the Lattice web site at
5.
Target Board Design Considerations
A 4.7K pull-down resistor is recommended on the TCK connection of the target board. This pull-down is recommended
to avoid inadvertent clocking of the TAP controller induced by fast clock edges or as VCC ramps up. This pull-down is
recommended for all Lattice programmable families.
The I
2
C signals SCL and SDA are open drain. A 2.2K pull-up resistor to VCC is required on the target board.
For Lattice device families that feature low power, it is recommended to add a 500 Ω resistor between VCCJ and GND
during the programming interval when a USB programming cable is connected to a very low power board design. A
FAQ is available that discusses this in more depth at:
http://www.latticesemi.com/en/Support/AnswerDatabase/2/2/0/2205
The JTAG programming port speed may need to be governed when using the programming cables connected to
customer PCBs. This is especially important when there is long PCB routing or with many daisy-chained devices. The
Lattice programming software can adjust the timing of TCK applied to the JTAG programming port from the cable. This
low-precision port setting of TCK depends on many factors, including the PC speed and the type of cable used (parallel
port, USB or USB2). This software feature provides an option to slow the TCK for debug or noisy environments. A FAQ is
available that discusses this in more depth at:
http://www.latticesemi.com/en/Support/AnswerDatabase/9/7/974.aspx
The USB download cable can be used to program Power Manager or ispClock products with Lattice programming
software. When using the USB cable with the Power Manager I devices, (POWR604, POWR1208, POWR1208P1), you
must slow do TCK by a factor of 2. A FAQ is available that discusses this in more depth at:
http://www.latticesemi.com/en/Support/AnswerDatabase/3/0/306.aspx