Lattice Semiconductor ASC Bridge Board, User Manual

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ASC Bridge Board
Evaluation Board User Guide
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FPGA-EB-02025-2.0 11
9. J1 Male Header
The J1 male header provides power pins and additional I/Os from either the MachXO3-9400 Development Board or the
ECP5 Versa Development Board’s expansion connector which are not connected to the ASC Breakout Board
connectors.
Table 9.1. J1 Male Header Connections for use with MachXO3-9400 or ECP5 Versa Develpment Board
J1 Pin
Number
Silkscreen
Name
MachXO3-9400 ECP5-45 FPGA Board
Signal Name
Ball Port Ball Port
1 +3.3 V –– –– ––
2 +2.5 V –– –– ––
3 N.C. –– –– ––
4 EXPCON_OSC (Note)
1
(Note)
2
EXPCON_OSC
5 EXPCON_CLKIN A10 PT23B A10 PT36A EXPCON_CLKIN
6 EXPCON_CLKOUT A21 PT44A E11 PT42B EXPCON_CLKOUT
7 HPE_RESOUT# G9 PT21D A8 PT18B HPE_RESOUT#
8 EXPCON_IO0 F8 PT11C A12 PT49A EXPCON_IO0
9 EXPCON_IO2 F9 PT21C B13 PT51A EXPCON_IO2
10 EXPCON_IO14 C6 PT14C A9 PT33A EXPCON_IO12
11 EXPCON_IO17 D8 PT15B B15 PT69A EXPCON_IO16
12 CARDSEL# C13 PT29C A7 PT18A CARDSEL#
13 GND –– –– GND
14 GND –– –– GND
15 GND –– –– GND
16 GND –– –– GND
17 GND –– –– GND
18 GND –– –– GND
19 GND –– –– GND
20 GND –– –– GND
21 GND –– –– GND
22 GND –– –– GND
23 GND –– –– GND
24 GND –– –– GND
Notes:
When using the MachXO3-9400 Development Board the J1 pin 4 signal EXPCON_OSC comes from either the on-board oscillator
Y2 or from an off-board source using J10.
When using the ECP5 Versa Development Board the J1 pin 4 signal EXPCON_OSC comes from the on-board Lattice
ispClock5406D device.