BT830 Hardware Integration Guide
Version 1.3
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
23
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Symbol
Parameter
Min
Typ
Max
Unit
t
ih
SCK high to SD_IN invalid hold time
0
-
-
ns
Figure 15: Digital Audio Interface Master Timing
P
OWER
S
UPPLY AND
R
EGULATION
BT830 can be powered by either of the two sources listed below:
Method #1 – Apply 3.3 V on pin-9, High-voltage linear regulator input (VREG_IN_HV), to generate the main 1.8
V out put on pin-10 (VREG_OUT_HV).
A minimum 1.5
μ
F capacitor must be connected to the Pin-10 (VREG_OUT_HV). Low ESR capacitors such as
multilayer ceramic types should be used. In this case, the VDD_PADS can be either 3.3V or 1.8V.
Method #2 – Apply 1.8V on pin-10 High-voltage linear regulator output (VREG_OUT_HV), to generate the
internal voltage for the system. Be sure to left Pin-9 un-connected in this method. In this case, the VDD_PADS
can only be set at 1.8V.
Note: The I/O signal voltage level (VDD_PADS) should be equal or less than the power supply mentioned voltage
above.
Voltage Regulator Enable and Reset
A single pin, VREG_EN_RST#, controls both the high-voltage linear regulator enables and the digital reset function.
The VREG_EN_RST# pin remains active controlling the reset function if the HV linear regulator is not used; the pin
must be driven high to take the device out of reset.
The regulator is enabled by taking the VREG_EN_RST# pin above 1.0V. The regulator can also be controlled by the
software.
The VREG_EN_RST# is also connected internally to the reset function, and is powered from the VDD_PADS supply, so
voltages above VDD_PADS must not be applied to this pin. The VREG_EN_RST# pin is pulled down internally.
The VREG_EN_RST# pin is an active low reset. Assert the reset signal for a period greater than five milliseconds to
ensure a full reset.
