Laird BT830-SA, Hardware Integration Manual

Page: 17 / 40

BT830 Hardware Integration Guide
Version 1.3
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth 17 Laird Technologies
Americas: +1-800-492-2320
Europe: +44-1628-858-940
Hong Kong: +852-2923-0610
PCM Timing Information
Table 10: PCM Timing information
Symbol
Parameter Min Typ Max Unit
f
mclk PCM_CLK frequency
4MHz DDS generation. Frequency
selection is programmable.
-
128
- kHz 256
512
48MHz DDS generation. Frequency
selection is programmable.
2.9 - - kHz
-
PCM_SYNC frequency for SCO connection - 8 - kHz
t
mclkh
(a)
PCM_CLK high 4MHz DDS generation 980 - - ns
t
mclkl
a)
PCM_CLK low 4MHz DDS generation 730 - - ns
-
PCM_CLK jitter 48MHz DDS generation - - 21
ns
pk-pk
t
dmclksynch
Delay time from
PCM_CLK high to
PCM_SYNC high 4MHz DDS generation - - 20 ns
48MHz DDS generation - - 40.83 ns
t
dmclkpout Delay time from PCM_CLK high to valid PCM_OUT - - 20 ns
t
dmclklsyncl
Delay time from
PCM_CLK low to
PCM_SYNC low (long
frame sync only) 4MHz DDS generation - - 20 ns
48MHz DDS generation - - 40.83 ns
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Table 11: PCM Master Mode Timing Parameters
Symbol Parameter Min Typ Max Unit
t
dmclkhsyncl
Delay time from
PCM_CLK high to
PCM_SYNC low 4MHz DDS generation - - 20 ns
48MHz DDS generation - - 40.83 ns
t
dmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
- - 20 ns
t
dmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT
high impedance
- - 20 ns
t
supinclkl
Set-up time for PCM_IN valid to PCM_CLK low 20 - - ns
t
hpinclkl
Hold time for PCM_CLK low to PCM_IN invalid 0 - - ns