BT800 Hardware Integration Guide
Version 0.2
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19
CONN-GUIDE-BT800_v0_2
k
t
dmclksy
nch
Delay time from
PCM_CLK high to
PCM_SYNC high
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
t
dmclkpo
ut
Delay time from PCM_CLK high to valid PCM_OUT
-
-
20
ns
t
dmclklsy
ncl
Delay time from
PCM_CLK low to
PCM_SYNC low (long
frame sync only)
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Table 10: PCM Master Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
t
dmclkhsyncl
Delay time from
PCM_CLK high to
PCM_SYNC low
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
t
dmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
-
-
20
ns
t
dmclkhpout
z
Delay time from PCM_CLK high to PCM_OUT
high impedance
-
-
20
ns
t
supinclkl
Set-up time for PCM_IN valid to PCM_CLK low
20
-
-
ns
t
hpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
0
-
-
ns
Figure 9: PCM Master Timing Long Frame Sync
