L-Card ADC Series, User Manual, Page: 23 / 69

Fig. 3-3. The principle of obtaining ADC data (in detail)
From
fig. 3-3
it also follows that the set non-zero interframe delay actually increases the settling
time for the first logical channel. This can be used, for example, by associating the first logical channel
with the physical channel to which the signal source is connected by the largest impedance.
It can be argued that by setting optimal n
su
/ n
av
settings for each channel, we are trying to
optimize the timing of the signal conditioning associated with the inter-channel passage and the
resolution of the ADC.
It is important to note that in the E-502, the ADC averaging algorithm described here (by the
simple average method) is considered as an inseparable part of the analog-to-digital converter itself,
although physically the averaging procedure is performed by means of FPGA using 24-bit integer
arithmetic.
Such an averaging operation increases the real resolution of the ADC by suppressing the
random components of the signal of different nature, improves the signal/noise by suppressing
the high-frequency components of the spectrum above the Nyquist frequency of 0.5*f
ch
for a
given physical channel associated with one (or more) logical channel. Note in passing that digital
filtering by the Blackfin processor (or high-level software) has a fundamentally different active
filtering area, because it is below the Nyquist frequency.
Once again, we emphasize that "by default" in the E-502 settings n
av
=1 is set, and "averaging"
does not occur by default.
3.3.7. Relative switching delays in ADC channels.
This information will be important only for that class of multi-channel data acquisition tasks
where the magnitude of the relative signal delay between the ADC channels is important for
measuring relative phase delays. For this class of problems, the theoretical calculated latency values
in the ADC channels are taken into account in the delay equalization algorithm based on one or
another method of signal interpolation.
1 2 1 3 2
Канал 1
Канал 2
Канал 3
t
k
n
k
=3 n
d
=2
t
d
t
k
t
ch
n
sw
=3
Кадр
Межкадровая
задержка
Кадр
Межкадровая
задержка
n
av
=1
n
av
=2
n
av
=3
n
su
=2
n
su
=1
n
su
=0
Номер
логического
канала АЦП
Момент сэмплирования одиночного отсчёта данных АЦП
Моменты сэмплирования отсчётов данных АЦП и выдача усредненного отсчёта
Отброшенный отсчёт данных АЦП
t
ref
t
sw
3 1
ADC logical
channel
number
Sampling time of ADC data single sample
Sampling time of ADC data and output of averaged readout
Discarded ADC data sample
Interframe
delay
Interframe
delay
Frame
Frame
Channel 1
Channel 2
Channel 3