L-Card ADC Series, User Manual, Page: 21 / 69

Fig. 3-2. Synchronization system structure in E-502
3.3.5.2. Secondary synchronization.
!
The functionality of the secondary synchronization is embedded in the project,
but is not currently implemented. You can find out about the availability of this
functionality
in the sales department of L-Card .
The secondary synchronization circuit ( II ) is the ADC data selection circuit depending on
the secondary synchronization conditions, operating exclusively against the background of the
previously started clock signal from the output of the primary synchronization circuit (
I ), i.e. against
the background of the started data stream of the ADC.
The following ADC data resolution synchronization modes are supported:
•
No synchronization (transparency mode)
•
Synchronization from an analog signal in the selected ADC channel
•
Digital synchronization with the selected signal from the inputs DI1 ... DI16, or
DI_SYN1, or DI_SYN2
The following modes of sensitivity to the fluctuations of the synchronization signal are
supported:
•
Enable of ADC data on the edge (drop) of an analog or digital signal
•
Enable of ADC data at a level "above the threshold" or "below the threshold" (for analog
synchronization) or at the logic level "1" (for digital synchronization)
The following ADC data inhibit modes are supported:
•
Software prohibition (stop) with the possibility of re-authorization (if the previously set
enable condition is repeated) without restarting the primary synchronization scheme
Узел
АЦП
Узел
ЦАП и
цифрового
вывода
Узел
цифр
.
ввода
Комму
-
татор
Схема
первичной
синхрони
-
зации
E-502
Генератор
f
ref
f
ref
Общие условия синхронизации всех процессов ввода-вывода
в E-502 (выбор опорной частоты и условий старта)
DI_SYN1
DI_SYN2
DI_SYN1
DI_SYN2
CONV_IN
START_IN
START_OUT
CONV_OUT
К ведомому
E-502
От ведущего
E-502
Внешняя
синхронизация
DI_SYN1
DI1...DI16
DI_SYN2
Управля
ющая
таблица
DAC2
DO1...DO16
DAC1
C
хема вторичной
синхронизации
данных АЦП
Поток данных “на ввод” Поток данных “на вывод”
Синхр.
Синхр.
Синхр.
Синхр.
X1...X16
Y1...Y16
GND32
2.0 / 1,5
МГц
Вход Выход
I
II
Схема селекции
данных АЦП в
зависимости
от вторичных
условий
синхронизации
Data flow "to input"
To E-502
slave
Scheme of ADC
data selection in
dependence
from the
secondary
synchronization
conditions
DAC and
digital
output node
Generator
Primary
synchroniz
ation
scheme
E-502
ADC secondary
synchronization
data scheme
Digital
input
node
Control
table
Switch ADC
node
MHz
External
synchronization
From the master
E-502
General synchronization conditions for all I/O processes
in E-502 (selection of reference frequency and start conditions)
Data flow "to output"
Output Input
Synch.
Synch.
Synch.
Synch.