Kyocera Mita FS-6750, Service Manual

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Operation theory
Engine controller system
4-27
FS-6750
The engine gate array
The engine gate array is a supplementary device to the Engine CPU. The gate
array is a CMOS type, 4100-gate, 100-pin QFP that has the following internal
blocks.
•
Address decoder
•
Registers
•
Interrupt handler
•
Ports A to F
•
Data selector
•
Overrun detector
•
Port mode controller
•
Kyocera I/F controller
•
Print density controller
•
Laser power controller
•
Decoder g/a flash
•
High-voltage clock generator
•
Test-print controller
•
Engine CPU address-hold controller
•
Interlock controller
Pin assignment
Pin assignment for the engine gate array is table on the following pages. The device
in Remarks column means those which the signal is forwarded to.
Table 4. 3 g/a pin assignment—1/4
Pin no. Signal In/Out Function Logic Remarks
1 VSS Power terminal (Ground)
2 SYSCLK OUT 4 MHZ clock output Engine CPU
3 TEST IN G/A test terminal
4 HEATON OUT Fuser heater output, H: On Neg.
5 FDON OUT Face down switching output, H: Face down
selected Neg. Fuser unit
6 FUON OUT Face up switching output, H: Face up selected Neg. Fuser unit
7 REGPAP IN Registration entry sensor paper detection input,
H: Paper detected Reg. sensor
8 TCOVOP IN Top cover open/close detection input, H: Open Top cover
9 FCOVOP* IN Feed unit open/close detection input, H: Open Feed cover
10 SCOVOP* IN Side cover open/close detection input, H: Open Side cover
11 VSS Power terminal (Ground)
12 RSVIO1 IN/OUT General-purpose input/output terminal 1 Fixed low
13 PAPER IN Cassette paper detection, H: Paper Cassette
14 HANDS* IN MP tray paper detection, H: Paper MP tray unit
15 TMOTON OUT Toner motor on output, H: On Neg. Developer