SMARC sXAL User Guide. Rev. 1.0
4/
System specifications
4.1.
Component Main Data
The table below summarizes the features of the motherboard.
Table 1: Component Main Data
SMARC sxal
Form factor
Smart Mobility ARChitecture (SMARC) Hardware with 82 mm x 50 mm, max. height 3
mm
Processor
The processor is Intel Apollo Lake which is a 14 nm / 24 x 31 mm Type 3; 0.594 mm pitch;
1296 pin count.
BIOS
Onboard 128Mb SPI flash for BIOS storage
Embedded
Controller
FPGA MAX10 for Embedded Feature set and logic control
Memory
1x LPDDR3L 1.35V Memory up to 8 GB, (ECC optional), eight plus one soldered chips
Storage
8 to 64 GB eMMC 5.0 Flash (option)
Watchdog Timer
Watchdog timer will be supported by WDT Out
Wake On
Wake on LAN
H/W Status
Monitor
The SMARC sxal design shall incorporate a Nuvoton NCT7802Y hardware monitor. It
delivers:
SM Bus connection to the System on Chip (SoC)
Fan control for on-board fan header
PWM and Tach interface to SMARC connector to satisfy SMARC specification
Temperature measurement of the SMARC PCB (2x with external thermal diode)
A/D measurements on V_RTC, V_3V3_S0 and V_3V0-525_IN
Trusted Platform
Module (TPM)
incorporated
Complex
Programmable
Logic Devices
(CPLD)
The SMARC sxal design shall incorporate a Altera MAX10 CPLD controller which will handle
the following.
Power Sequencing
Status and control signal level shifting mostly to allow signals routed to SMARC
connector to comply with SMARC Specifications.
Incorporated with a LPC to UART bridge to provide two 2-wire UART.
Incorporated with a LPC to I2C bridge to provide I2C interface.
Incorporated with a LPC to GPIO bridge to provide twelve GPIOs.
Power
management
C0, C1, C6, C7, C8, C9, C10
Expansion
The SOC provides four PCIe Gen 2 lanes that can be configured as 4 x 1 (i.e. 4 PCIe links that
are x1 wide) or as 1x4 (one link in an x4 configuration). The PCIe links and support signals
are to be implemented as per the SMARC specification document.
Operating System
Support
Windows® 10, Enterprise, Windows 10 IoT, Linux, VxWorks
External I/O
LAN, USB
one Gbit-Ethernet, two USB3.0 and four USB2.0
Audio
one High Definition Audio (HDA)
Display Port
one embedded Display Port (eDP) interface. The Intel SoC eDP port shall be used to create
the SMARC eDP interface which are sharing the same pins with the LVDS interface.
LVDS
The Intel SoC eDP shall be used to create the SMARC dual channel LVDS interface. The
interface should be able to support 18 and 24 bit single and dual channel LVDS panels.
Internal I/O: SMARC I/O System Interconnection
SATA
one Gen3 SATA link
