MOPSlcd6
BIOS-Description
p588m115.doc
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Industrielle Computertechnik AG
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Advanced Chipset Control sub menu:
Feature
Option
Description
AT bus clock frequency
7.16 MHZ
PCICLK/4
PCICLK/3
Allows to select ISA bus clock frequency.
NOTE: Some ISA devices might not work at
PCICLK/3 (11 MHz)!
Passive Release
Disabled
Enabled
Enables more efficient ISA Bus master cycles
to PCI.
Delayed Transaction
Disabled
Enabled
Latches PCI-to-ISA cycles into buffer to free
the PCI bus.
ISA Master Line Buffer
Disabled
Enabled
Enables ISA master line buffer to enhance
performance.
DMA Line Buffer
Disabled
Enabled
Enables DMA line buffer to enhance
performance.
PCI to ISA Posted Write Buffer Disabled
Enabled
Enables PCI to ISA posted write buffer.
Enable Memory Gap **
Disabled
Conventional
Extended
Turns system RAM of and frees address space
(512kB-640kB or 15MB-16MB) for use with an
option card.
CAS Latency
2
3
Select CAS Latency time.
SDRAM Timing *
3-6-9
3-5-8
3-4-7
2-5-7
Controls RAS pre-charge timing in HCLKIN’s.
tRP – tRAS – tRC
Pipe Function
Disabled
Enabled
Enables the asserting of NA (Next Address)
when the cycle is a L2 or DRAM access cycle.
Primary Frame Buffer
Disable, 1 MB,
2 MB
, 4 MB,
8 MB, 16 MB
Select the size of the primary frame buffer and
enables Host to PCI write buffer
VGA Frame Buffer
Disabled
Enabled
Enables burst PCI cycles for VGA fixed frame
buffer at A0000h – BFFFFh.
Data Merge
Disabled
Enabled
If enabled, only the words which address are
consecutive linear can be merged into one
line.
Byte Merge
Disabled
Enabled
Enables the byte-merge feature for frame
buffer cycles
Fast Back to Back
Disabled
Enabled
Enables PCI fast back to back capability.
PCI Write Burst
Disabled
Enabled
Enables PCI write burst capability.
*) default changed for P588R115 (was 3-4-7), **) P588R116 upwards
