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Kontron FlexATX-KBL-S-C236, User Manual

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Kontron FlexATX-KBL-S-C236 User Manual Download Page 69

FlexATX-KBL-S-C236 – Rev. 1.1 

 

 

www.kontron.com 

// 69 

 

Sub-Screen 

Function 

Description 

Lane 15 

Value for Lane 15 

Gen3 Endpoint Hint 
value for each Lane 

Lane 0 

Value for Lane 0 

Lane 1 

Value for Lane 1 

Lane 2 

Value for Lane 2 

Lane 3 

Value for Lane 3 

Lane 4 

Value for Lane 4 

Lane 5 

Value for Lane 5 

Lane 6 

Value for Lane 6 

Lane 7 

Value for Lane 7 

Lane 8 

Value for Lane 8 

Lane 9 

Value for Lane 9 

Lane 10 

Value for Lane 10 

Lane 11 

Value for Lane 11 

Lane 12 

Value for Lane 12 

Lane 13 

Value for Lane 13 

Lane 14 

Value for Lane 14 

Lane 15 

Value for Lane 15 

Gen3 RxCTLE Control 

Bundle0 

Gen3 RxCTLE setting for 
Bundle0 (Lane0, Lane1) 

Bundle1 

Gen3 RxCTLE setting for 
Bundle1 (Lane2, Lane3) 

Bundle2 

Gen3 RxCTLE setting for 
Bundle2 (Lane4, Lane5) 

Bundle3 

Gen3 RxCTLE setting for 
Bundle3 (Lane6, Lane7) 

Bundle4 

Gen3 RxCTLE setting for 
Bundle4 (Lane8, Lane9) 

Bundle5 

Gen3 RxCTLE setting for 
Bundle5 (Lane10, Lane11) 

Bundle6 

Gen3 RxCTLE setting for 
Bundle6 (Lane12, Lane13) 

Bundle7 

Gen3 RxCTLE setting for 
Bundle7 (Lane14, Lane15) 

RxCTLE Override 

When Enables, it overrides 
PEG’s RxCTLE adaptive 
behavior 

Always Attempt SW EQ 

Always Attempt SW EQ, 
even it has been done once 

Number of Presets to test 

Choose between 7, 3, 5, 8 
and 0-9. Auto = current 

Summary of Contents for FlexATX-KBL-S-C236

Page 1: ...USER GUIDE FlexATX KBL S C236 Doc Rev 1 1 Doc ID 1061 6791...

Page 2: ...FlexATX KBL S C236 Rev 1 1 www kontron com 2 This page has been intentionally left blank...

Page 3: ...ll be suitable for the specified use without further testing or modification Kontron expressly informs the user that this manual only contains a general description of processes and instructions which...

Page 4: ...s meet all applicable requirements Unless otherwise stated in the product documentation the Kontron device is not provided with error tolerance capabilities and cannot therefore be deemed as being eng...

Page 5: ...ty and the warranty period in your region visit http www kontron com terms and conditions Kontron sells products worldwide and declares regional General Terms Conditions of Sale and Purchase Order Ter...

Page 6: ...d or result in damage to your material Please refer also to the High Voltage Safety Instructions portion below in this section ESD Sensitive Device This symbol and title inform that the electronic boa...

Page 7: ...hernet Connectors I O area 25 6 4 USB Connectors I O area 26 6 5 Fan Connector internal J34 J35 28 6 6 Front Panel internal 29 6 7 USB3 0 Internal Header 29 6 8 Internal Feature Connector 30 6 9 Audio...

Page 8: ...s List 43 7 2 External indicators list 43 7 3 System Status LED 43 8 BIOS Setup structure 44 8 1 Main Setup Menu 44 8 2 Advanced Setup Menu 44 8 3 Chipset Setup Menu 58 8 4 Security Setup Menu 84 8 5...

Page 9: ...tor Definitions 23 Table 6 Processor Support 24 Table 7 Memory Support 24 Table 8 S PDIF 32 Table 9 LEDs internal 43 Table 10 External Indicators 43 Table 11 Main Setup Menu Sub Screens Functions 44 T...

Page 10: ...13 S PDIF and Lineout Header 32 Figure 14 LVDS Connector 32 Figure 15 SATA Connector 33 Figure 16 Available Cable Kit 33 Figure 17 SATA Power Internal Connector 34 Figure 18 52 pin PCIe x1 connector 3...

Page 11: ...n describing the FlexATX KBL S board s special features and is not intended to be a standard PC textbook New users are recommended to study the short installation procedure stated in the following cha...

Page 12: ...essor range up to 80 W Thermal Design Power TDP Chipset Kabylake C236 PCH 2x ECC NON ECC SODIMM Memory Architecture Two Display Ports DP and and LVDS or optional three DPs Four Gigabit Ethernet Ports...

Page 13: ...n be skipped 1 Turn off the PSU Power Supply Unit Turn off PSU completely no mains power connected to the PSU or leave the Power Connectors unconnected while configuring the board Otherwise components...

Page 14: ...byLake motherboard should be above or equal to 473 W 3 3 Requirements IEC60950 1 Take care when designing chassis interface connectors in order to fulfil the IEC60950 1 standard Users of FlexATX KBL S...

Page 15: ...losi n si la bater a se sustituye incorrectamente Sustituya solamente por el mismo o tipo equivalente recomendado por el fabricante Disponga las bater as usadas seg n las instrucciones del fabricante...

Page 16: ...FlexATX KBL S C236 Rev 1 1 www kontron com 16 4 System specifications 4 1 Block Diagram Figure 1 Block Diagram of FlexATX KBL...

Page 17: ...to 2400 MT s max up to 32 GB memory using 2x16 GB modules Storage 4x SATA 3 0 with 6 Gb s 2x SATA optional one M 2 card slot optional Watchdog Timer Implemented in embedded controller IT8528E H W Sta...

Page 18: ...2 1 OpenCL 2 0 OpenCL 1 2 Supports full HW accelerated video decoding for AVC VC1 MPEG2 HEVC VP8 JPEG Supports full HW accelerated video encode for AVC MPEG2 HEVC VP8 Switchable Hybrid graphics when...

Page 19: ...rd Immunity for industrial environment IEC 61000 PT4 2 EN 61000 4 2 Eletrostatic discharge immunity ESD IEC 61000 PT4 3 EN 61000 4 3 and ENV 50204 Radiated field IEC 61000 PT4 4 EN 61000 4 4 Electrica...

Page 20: ...it from the jumper pins according to the following instructions Here NC stands for Not Connect 5 1 1 Connectors Table 4 Connectors Connectors Function Remark CPU_FAN CPU FAN Connector 1 x 4 Wafer SYS...

Page 21: ...l connector 7 SATA power connector 8 PCH controller 9 USB 3 0 10 MiniPCIE 11 LPC Header 12 PCIeX4 13 PCIeX1 14 Feature Connector 15 Buzzer 16 LVDS Connector 17 ATX 4 pin Power connector 18 CPU connect...

Page 22: ...FlexATX KBL S C236 Rev 1 1 www kontron com 22 5 3 Rear Side Figure 3 Rear Side...

Page 23: ...hmitt trigger input TTL compatible IOC Input open collector Output TTL compatible IOD Input Output CMOS level Schmitt triggered Open drain output NC Pin not connected O Output TTL compatible OC Output...

Page 24: ...W 100 C 1060 9525 Core i3 7101E 3 9 GHz Yes 3 MB SR32Z 54 W 100 C 1060 9524 Xeon E3 1275 V6 3 8 GHz 4 2 GHz Yes 8 MB SR32A 73 W 1060 9489 6 2 System Memory Support The memory system has two DDR4 sock...

Page 25: ...se TX In MDI crossover mode this pair acts as the BI_DB pair and is the receive pair in 10Base T and 100Base TX MDI 1 MDI 1 In MDI mode this is the second pair in 1000Base T i e the BI_DB pair and is...

Page 26: ...ceive transmit data lines n 0 1 2 3 5 V SB5 V 5 V supply for external devices SB5 V is supplied during power down to allow wakeup on USB device activity Protected by resettable 2 6 A of USB3 0 and 1 5...

Page 27: ...kontron com 27 For SuperSpeed rates it is required to use a USB cable which is specified in USB3 0 standard Figure 7 USB 3 0 High Speed Cable UTP Signal Pair SDP Signal Pair Jacket Ground Filler optio...

Page 28: ...o implement FAN speed control Figure 8 4 pin Fan Connector Pin Signal Description Type 1 PWM FAN speed sense O 2 TACHO FAN speed control I 3 12 V Power 12 V PWR 4 GND Ground PWR Signal Description Typ...

Page 29: ...S0 12 Power 5 0V S0 13 SATA LED output Active low 14 Suspend LED output 15 Ground 16 Power button input Active low 17 Reset button input Active low 18 Ground 19 Power 3 3V S5 20 Headphone out right 21...

Page 30: ...tery 7 N C 8 N C 9 Power 3 3V S5 10 Power 5 0V S5 11 GPIO0 12 GPIO1 13 GPIO2 14 GPIO3 15 GPIO4 16 GPIO5 17 GPIO6 18 GPIO7 19 Ground 20 Ground 21 GPIO8 22 GPIO9 23 GPIO10 24 GPIO11 25 GPIO12 26 GPIO13...

Page 31: ...dphone max 1 6 VRMS Ring Front R OA For headphone max 1 6 VRMS Sleeve GND PWR Pin Designation Signal Type Note Tip LINE1_L IA 1 0 VRMS 30 k Ring LINE1_R IA 1 0 VRMS 30 k Sleeve GND PWR Pin Designation...

Page 32: ...2 Power 12 0V S0 3 Power 12 0V S0 4 Power 12 0V S0 5 Power 12 0V S0 6 Ground 7 Power 5 0V S0 8 Ground 9 Power LVDS Logic 10 Power LVDS Logic 11 DDC Clock 12 DDC Data 13 Backlight Control PWM 14 VDD E...

Page 33: ...Clock 36 LVDS Channel B Clock 37 LVDS Channel B Data3 38 LVDS Channel B Data3 39 Ground 40 Ground 6 12 SATA Serial ATA Disk Interfaces internal Figure 15 SATA Connector Pin Signal Type 1 GND PWR 2 SAT...

Page 34: ...Power SATA_PWR Pin Signal 1 12V 2 GND 3 GND 4 VCC5 6 14 PCIe x1 connector 1 J2 Figure 18 52 pin PCIe x1 connector Pin Signal Pin Signal A1 PRSNT1 B1 V_12V0_S0 A2 V_12V0_S0 B2 V_12V0_S0 A3 V_12V0_S0 B3...

Page 35: ...Pin Signal 1 WAKE 2 3 3V_S5 3 N C 4 GND 5 N C 6 1 5V_S0 7 CLKREQ 8 UIM PWR 9 GND 10 UIM DATA 11 PCIe_REFCLK 12 UIM CLK 13 PCIe_REFCLK 14 UIM RST 15 GND 16 UIM VPP 17 UIM C8 18 GND 19 UIM C4 20 W_DISA...

Page 36: ...V output is electronically fused to 900 mA each port Figure 20 Double USB 3 0 Connector Pin Signal Remark 1 VBUS 5V 900mA max Low Full High Speed USB 2 0 contact pins Bottom con 2 USB Data 3 USB Data...

Page 37: ...Pin Signal 1 ML LANE 0 2 GND ML LANE 0 3 ML LANE 0 4 ML LANE 1 5 GND ML LANE 1 6 ML LANE 1 7 ML LANE 2 8 GND ML LANE 2 9 ML LANE 2 10 ML LANE 3 11 GND ML LANE 3 12 ML LANE 3 13 AUX_SEL 14 Pull down to...

Page 38: ...ier power 2 GND 3 N C Not connected 4 GND 6 20 Internal Power Connector Figure 24 Internal Power Connector Pin Signal Pin Signal 1 Power Input 3 3V S0 13 Power Input 3 3V S0 2 Power Input 3 3V S0 14 P...

Page 39: ...ed Power Supply for KabyLake motherboard should be above or equal to 473 W 6 21 PS 2 Header J30 Figure 25 PS 2 Header Pin Signal 1 Keyboard Clock 2 Keyboard Data 3 Mouse Clock 4 Mouse Data 5 Power 5 0...

Page 40: ...9 N C 20 N C 6 23 SPI External Flash header J36 Figure 27 12 pin SPI Header Pin Signal Pin Signal 1 SPI Clock 2 Power 3 3V S5 3 SPI CS 4 SPI ADDIN 5 Power 3 3V S5 6 N C 7 SPI MOSI 8 SPI ISOLATE 9 SPI...

Page 41: ...I MISO 10 Ground 11 SPI IO2 12 SPI IO3 6 25 RS 485 RS 422 Header J28 Figure 29 5 pin RS 485 RS 422 Header Pin Signal 1 TX1 2 RX1 3 TX1 4 RX1 5 Ground 6 26 RS 232 Header J27 Figure 30 10 pin RS 232 Hea...

Page 42: ...KBL S C236 Rev 1 1 www kontron com 42 6 27 RTC SRTC Reset Jumper J45 J46 Figure 31 2 pin RTC Reset Jumper RTC Reset Jumper J45 Pin Signal 1 RTCRST 2 Ground SRTC Reset Jumper J46 Pin Signal 1 SRTCRST 2...

Page 43: ...GbE Link Activity Right LED GbE Speed 100 1000 J4 Left LED GbE Link Activity Right LED GbE Speed 100 1000 7 2 External indicators list Table 10 External Indicators Location Indicator Function J25 SATA...

Page 44: ...menu sub screens and provides basic system information as well as functions for setting the system time and date Table 11 Main Setup Menu Sub Screens Functions Sub Screen Function Description BIOS In...

Page 45: ...dware Prefetcher Adjacent Cache Line Prefetch To turn on off prefetching of adjacent cache lines Intel VMX Virtualization Technology Enable Disable Intel VMX Virtualization Technology PECI Enable Disa...

Page 46: ...ble Disable Auto Voltage Optimization Power Performance CPU Power Managemen t Control Boot Performance mode Select the performance state that the BIOS will set starting from reset vector Intel R Speed...

Page 47: ...ettings Up ConfigTDP Level 2 Setting for Power Limit 1 Power Limit 2 Power Limit 1 Time Window ConfigTDP Turbo Activation Ratio CPU VR Settings PSYS Slope Display PSYS Slope PSYS Offset Display PSYS O...

Page 48: ...R Current Limit VR Voltage Limit Display VR Voltage Limit TDC Enable Enable Disable TDC TDC Current Limit Display TDC Current Limit TDC Time Windows TDC Time Window value in milliseconds 1ms is defaul...

Page 49: ...Limit VR Voltage Limit Display VR Voltage Limit TDC Enable Enable Disable TDC TDC Current Limit Display TDC Current Limit TDC Time Windows TDC Time Window value in milliseconds 1ms is default Range f...

Page 50: ...DC Time Window value in milliseconds 1ms is default Range from 1ms to 10ms except for 9ms as it has no valid encoding in the MSR definition TDC Lock Enable Disable TDC Lock VR Mailbox Command options...

Page 51: ...ect for Logical Interrupts Timed MWAIT Enable Disable Timed MWAIT Custom P state Table Display Number of P states Energy performance gain Enable Disable Energy performance gain EPG DIMM Idd3N Display...

Page 52: ...Progress to receive PET Events Watchdog Enable Disable Watchdog Timer OS Timer Display OS Timer BIOS Timer Display BIOS Timer Secure Erase Configuration Secure Erase Mode Change Secure Erase module b...

Page 53: ...placement polling loop ME DID Message Enable Disable ME DID Message HECI Retry Disable Setting this option disables retry mechanism for all HECI APIs HECI Message check Disable Setting this option dis...

Page 54: ...k WWAN Enable Disable RTD3 support for WWAN Sata Port 0 Setup option to control the SATA port RTD3 functionality Sata Port 1 Setup option to control the SATA port RTD3 functionality Sata Port 2 Setup...

Page 55: ...trol Select COM1 receiver termination Direction Control Select COM1 direction Serial Port 2 Configuration Serial Port Enable Disable Serial Port COM Device Settings Display Device Settings Change Sett...

Page 56: ...col Policy Intel R GOP Driver Shows GOP Driver Version Output Select Output Interface PCI Subsystem settings AMI PCI Driver Version Shows AMI PCI Driver Version Above 4G Decoding Enable Disable Above...

Page 57: ...n name Swapped swap odd bus signals with even bus signals Clock Frequency Center Spread Programmable center spreading of pixel clock frequency to minimize EMI Differential Output Swing Level Programma...

Page 58: ...nu provides information about the configuration Table 13 Chipset Setup Menu Functions Sub Screen Function Description System Agent SA Configuration Memory Configuration Memory Thermal Configuratio n M...

Page 59: ...Register s Enabled lock several PCU registers related to DDR power thermal management Extern Therm Status Enabled The value from EXTTS is used Disabled Pcode ignores the EXTTS Closed Loop Therm Manag...

Page 60: ...Budget Ch0 Dimm0 Range 255 0 31 875 0 in W for OLTM 127 5 0 in C for CLTM Warm Budget Ch0 Dimm1 Range 255 0 31 875 0 in W for OLTM 127 5 0 in C for CLTM Hot Budget Ch0 Dimm0 Range 255 0 31 875 0 in W...

Page 61: ...L 2 Power Range 0 2 14 1 2047 875 0 in W 0 Def RAPL PL 2 Window X Power PL 2 time windowX value 1 1024 1 x 4 2 y 0 Def RAPL PL 2 Window Y Power PL 2 time windowY value 1 1024 1 x 4 2 y 0 Def Memory Th...

Page 62: ...Enable Disable DIMM RON Training Write Drive Strenght Equalization 2D Enable Disable Write Drive Strenght Equalization 2D Write Slew Rate Training Enable Disable Write Slew Rate Training Read ODT Trai...

Page 63: ...ing Enable Disable CMD Slew Rate Training CMD Drive Strength Tx Equalization Enable Disable CMD Drive Strength Tx Equalization CMD Normalization Enable Disable CMD Normalization Memory Configuration D...

Page 64: ...le VC1 Read Metering Feature RdMeter VC1 RdMeter Time Window VC1 Read Metering Time Window time window over which VC1 read request counter is tracked VC1 RdMeter Threshold VC1 Read Metering Threshold...

Page 65: ...ration Graphics Turbo IMON Current Graphics turbo IMON current values supported 14 31 Skip Scanning of External Gfx Card If Enable it will not scan for External Gfx Card on PEG and PCH PCIE Ports Exte...

Page 66: ...erform Gen3 Equalization Phase 2 DMI Gen3 Eq Phase 3 Method Select Method for Gen3 Equalization Phase 3 DMI Vc1 Control Enable Disable DMI Vc1 DMI Vcm Control Enable Disable DMI Vcm Program Static Pha...

Page 67: ...wer limit value PEGO Physical Slot Number Set the physical slot number attached to this port PEGO Hotplug PCI Express Hot Plug Enable Disable PEG 0 1 1 Enable Root Port Enable Disable the Root Port Ma...

Page 68: ...5 Value for Lane 5 Lane 6 Value for Lane 6 Lane 7 Value for Lane 7 Lane 8 Value for Lane 8 Lane 9 Value for Lane 9 Lane 10 Value for Lane 10 Lane 11 Value for Lane 11 Lane 12 Value for Lane 12 Lane 13...

Page 69: ...alue for Lane 14 Lane 15 Value for Lane 15 Gen3 RxCTLE Control Bundle0 Gen3 RxCTLE setting for Bundle0 Lane0 Lane1 Bundle1 Gen3 RxCTLE setting for Bundle1 Lane2 Lane3 Bundle2 Gen3 RxCTLE setting for B...

Page 70: ...search error target value 1 65535 Generate BDAT PEG Margin Data Enable to generate BDAT PCIe margin tables PCIe Rx CEM Test Mode Enable Disable PEG Rx CEM Loopback Mode PCIe Spread Spectrum Clocking A...

Page 71: ...W A for bad USB device s connected behind PCIE PEG Port PCIe Function swap When Disabled prevents PCIE rootport function swap PCI Express Gen3 Eq Lanes PCIE1 Cm Display PCIE1 Cm PCIE1 Cp Display PCIE1...

Page 72: ...19 Cm Display PCIE19 Cm PCIE19 Cp Display PCIE19 Cp PCIE20 Cm Display PCIE20 Cm PCIE20 Cp Display PCIE20 Cp Overrides SW EQ settings Enable Disable Overrides SW EQ settings PCI Express Root Port x x 1...

Page 73: ...on Correctable Error Enable Disable PME SCI PCI Express PME SCI Enable Disable Hot Plug PCI Express Hot Plug Enable Disable Advanced Error Reporting Enable Disable Advanced Error Reporting PCIe Speed...

Page 74: ...lignment 0 31 bits Prefetchable Memory Alignment Prefetchable Memory Alignment 0 31 bits SATA and RST Configuration SATA Controller s Enable Disable SATA Port SATA Mode Selection Determine How SATA co...

Page 75: ...alue SATA1 mSATA Software Preserve Unknown Software Preserve Port 1 Enable Disable SATA Port Hot Plug Designates this port as Hot Pluggable Configured as eSATA Hot Plug Supported Spin Up Device Enable...

Page 76: ...Value SATA3 J12 Software Preserve Unknown Software Preserve Port 3 Enable Disable SATA Port Hot Plug Designates this port as Hot Pluggable Configured as eSATA Hot Plug Supported Spin Up Device Enable...

Page 77: ...ware Preserve Port 7 Enable Disable SATA Port Designates this port as Hot Pluggable Configured as eSATA Hot Plug Supported Spin Up Device Enable Disable Spin Up Device SATA Device Type Identify the SA...

Page 78: ...ables installed will be used iDisplay Audio Disconnect Disconnects SDI2 signal to hide disable iDisplay Audio Codec PME Enable Enables PME wake of HD Audio controller during POST HD Audio Advanced Con...

Page 79: ...ost process Enables Disables 3rd Party Processing Module Support identified by GUID DTS Enables Disables 3rd Party Processing Module Support identified by GUID IntelSST Speech Enables Disables 3rd Par...

Page 80: ...le Enables Disables 3rd Party Processing Module Support identified by GUID Icepower IP EFX sub module Enables Disables 3rd Party Processing Module Support identified by GUID Icepower IP SFX sub module...

Page 81: ...r Connected Device Indicate what type of device is connected to this serial IO controller Serial IO SPI0 Settings ChipSelect Polarity Sets initial polarity for ChipSelect signal Serial IO UART0 Settin...

Page 82: ...s user consent to enable the DCI which allows debug over the USB3 interface DCI Auto Detect Enable When set to Auto Detect it detect DCI being connected during BIOS post time and enables DCI Debug Por...

Page 83: ...rt 80h behind LPC Compatible Revision ID Enable Disable the PCH Compatible Revision ID feature PCH Cross Throttling Enable Disable PCH Cross Throttling feature Disable energy reporting Enable Disable...

Page 84: ...0 UEFI Spec Version Select TCG2 Spec Version support Physical Presence Spec Version Select PPI Spec Device Select Select TPM Device 1 2 or 2 0 or Auto Select Intel BIOS Guard Technology Intel BIOS Gua...

Page 85: ...boot device priority order which is dynamically generated Table 15 Boot Priority Order Function Description Boot Configuration Setup Prompt Timeout Number of seconds to wait for setup activation key...

Page 86: ...ption Discard Changes Discard changes done so far to any of the setup option Restore Defaults Restore Load Default values for all the setup option Save as User Defaults Save the changes done so far as...

Page 87: ...General Purpose Input Output HD Hard Disk PCIe PCI Express PECI Platform Environment Control Interface RTC Real Time Clock SATA Serial ATA SELV Safety Extra Low Voltage SPI Serial Peripheral Interfac...

Page 88: ...f employees in research and development Kontron creates many of the standards that drive the world s embedded computing platforms bringing to life numerous technologies and applications that touch mil...

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