CP3005-SA – Rev. 0.6 Preliminary
// 32
4/
Configuration
4.1.
DIP Switch Configuration
The quad DIP switch SW1 provides the following switches for board configuration: POST code indication, SPI boot
flash selection, and uEFI BIOS configuration.
Figure 6: DIP Switch SW1
Table 11: DIP Switch SW1 Functionality
Switch
Setting
Functionality
1
OFF
Boot-up with POST code indication on LED3..0
ON
Boot-up without POST code indication on LED3..0
2
OFF
Boot from the standard SPI boot flash
ON
Boot from the recovery SPI boot flash
3
OFF
Standard QM370 reset implementation
ON
Reset does a power cycle (reset event drops the QM370
PWROK input)
4
OFF
Boot using the currently saved uEFI BIOS settings
ON
Clear the uEFI BIOS settings and use the default values
The default setting is indicated by using bold fonts.
To clear the uEFI BIOS settings and the passwords, proceed as follows:
1.
Set DIP switch SW1, switch 4, to the ON position.
2.
Apply power to the system.
3.
Wait 30 seconds and then remove power from the system. During this time period no messages are
displayed.
4.
Set DIP switch SW1, switch 4, to the OFF position.
4.2.
System Write Protection
The CP3005-SA provides write protection for non-volatile memories via the onboard configuration resistor JMP2
(R242) (only available upon request), the uEFI Shell, and the CompactPCI rear I/O connector J2, pin B15
(REAR_FANSENSE_SYS_WP#). If one of these sources is enabled, the system is write protected. Please contact
Kontron for further information before using these functions.
