Kontron COMe-cBT6, User Manual

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COMe-cBT6 / User Guide
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A58 P PCI Express Lane 3 Tr DP-O - only available on no-LAN var.
A59 PCIE_TX3- PCI Express Lane 3 Transmit - DP-O - only available on no-LAN var.
A60 GND Power Ground PWR GND - -
A61 P PCI Express Lane 2 Tr DP-O - -
A62 PCIE_TX2- PCI Express Lane 2 Transmit - DP-O - -
A63 GPI1 General Purpose Input 1 I-3.3 PU 100k 3.3V (S0) -
A64 P PCI Express Lane 1 Tr DP-O - -
A65 PCIE_TX1- PCI Express Lane 1 Transmit - DP-O - -
A66 GND Power Ground PWR GND - -
A67 GPI2 General Purpose Input 2 I-3.3 PU 100k 3.3V (S0) -
A68 P PCI Express Lane 0 Tr DP-O - -
A69 PCIE_TX0- PCI Express Lane 0 Transmit - DP-O - -
A70 GND Power Ground PWR GND - -
A71 LVDS Channel A DAT0+ DP-O - -
A72 LVDS_A0- LVDS Channel A DAT0- DP-O - -
A73 LVDS Channel A DAT1+ DP-O - -
A74 LVDS_A1- LVDS Channel A DAT1- DP-O - -
A75 LVDS Channel A DAT2+ DP-O - -
A76 LVDS_A2- LVDS Channel A DAT2- DP-O - -
A77 LVDS_VDD_EN LVDS Panel Power Control O-3.3 PD 100k -
A78 LVDS Channel A DAT3+ DP-O - -
A79 LVDS_A3- LVDS Channel A DAT3+ DP-O - -
A80 GND Power Ground PWR GND - -
A81 LV LVDS Channel A Clock+ DP-O - 20-80MHz
A82 LVDS_A_CK- LVDS Channel A Clock- DP-O - 20-80MHz
A83 LVDS_I2C_CK LVDS I2C Clock (DDC) IO-3.3 PU 2k21 3.3V (S0) -
A84 LVDS_I2C_DAT LVDS I2C Data (DDC) IO-3.3 PU 2k21 3.3V (S0) -
A85 GPI3 General Purpose Input 3 I/O-3.3 PU 100k 3.3V (S0) -
A86 RSVD Reserved for future use nc - -
A87 RSVD Reserved for future use nc - -
A88 PCIE0 Reference PCI Express Clock + DP-O - 100MHz
A89 PCIE0_CK_REF- Reference PCI Express Clock - DP-O - 100MHz
A90 GND Power Ground PWR GND - -
A91 SPI_POWER 3.3V Power Output Pin for external SPI flash O-3.3 - 100mA (max.)
A92 SPI_MISO SPI Master IN Slave OUT I-3.3 PD 20k in CPU (SPI) All SPI signals are tri-stated with 20k ohm CPU internal
weak pull-up until reset is deasserted
A93 GPO0 General Purpose Output 0 O-3.3 PD 100k -
A94 SPI_CLK SPI Clock O-3.3 PD 20k in CPU (SPI) All SPI signals are tri-stated with 20k ohm CPU internal
weak pull-up until reset is deasserted
A95 SPI_MOSI SPI Master Out Slave In O-3.3 PD 20k in CPU (SPI) All SPI signals are tri-stated with 20k ohm CPU internal
weak pull-up until reset is deasserted
A96 TPM_PP TPM Physical Presence nc - TPM_PP not supported by used TPM
A97 TYPE10# Indicates TYPE10# to carrier board nc - -
A98 SER0_TX Serial Port 0 TXD O-3.3 - 20V protection circuit implemented on module, PD on
carrier board needed for proper operation
A99 SER0_RX Serial Port 0 RXD I-5T PU 47k 3.3V (S0) 20V protection circuit implemented on module
A100 GND Power Ground PWR GND - -
A101 SER1_TX Serial Port 1 TXD O-3.3 - 20V protection circuit implemented on module, PD on
carrier board needed for proper operation
A102 SER1_RX Serial Port 1 RXD I-5T PU 47k 3.3V (S0) 20V protection circuit implemented on module
A103 LID# LID Switch Input I-3.3 PU 47k 3.3V (S5) 20V protection circuit implemented on module
A104 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A105 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A106 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A107 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A108 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A109 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A110 GND Power Ground PWR GND - -