TK-80
10
CIRCUIT DESCRIPTION
1. Frequency Configuration
The TK-80 uses double conversion in all modes.
Mode
Display frequency
USB/LSB
Carrier point frequency
CW
Transmission carrier frequency
AM
Transmission carrier frequency
FSK
Mark transmission frequency
AFSK
Carrier point frequency
Table 1
Display frequency in each mode
The receiver frequency in SSB mode is given by the fol-
lowing equation when the receiver tone produced by the in-
put frequency (f
IN
) from the antenna is zero beat (when an
SSB signal with a carrier point of fIN is zeroed in):
f
IN
= f
LO1
– f
LO2
– f
CAR
.................... (1)
73.045MHz
TX MIX-2
RX MIX-1
TX MIX-1
RX MIX-2
B.M
DET
ANT
10.695MHz
73.045MHz
MIC IN
AF OUT
fin
LO1
LO2
CAR
73.145~
103.045MHz
62.35MHz
10.695MHz
Since all these frequencies are generated by the PLL cir-
cuit, as shown in Figure 2 (PLL circuit frequency configura-
tion), the receiver frequency is determined only by the refer-
ence frequency, f
STD
, and the PLL divide ratio. This means
the accuracy of the reference frequency determines the ac-
curacy of the operating frequency of the transceiver.
The accuracy of the reference crystal oscillator used in the
TK-80 is 10ppm (–10
°
C to +50
°
C). The accuracy of the op-
tional temperature-compensated crystal oscillator (TCXO SO-
2) is 0.5ppm (–10
°
C to +50
°
C).
In SSB transmission mode or in other modes, the fre-
quency is determined by the reference frequency (f
STD
and
the PLL divide ratio). Table 1 lists the display frequencies in
the various modes.
The pitch of the incoming signal in CW mode can be varied
in 50Hz steps in the range of 400 or 800Hz without changing
the center frequency of the IF filter (variable CW pitch sys-
tem).
2. PLL Circuit Configuration
The TK-80 PLL circuit uses a reference frequency of
20MHz, and covers 100kHz to 30MHz. Figure 2 shows a PLL
block diagram and frequency configurations.
2-1. Reference oscillator circuit
The reference frequency (f
STD
) for frequency control is
generated by the 20MHz crystal oscillator, X501 and Q525.
The 20MHz reference frequency is supplied to DDS IC500
and IC501 and PLL IC502.
The crystal oscillator circuit can be replaced by an optional
TCXO (SO-2 or accessory of KPE-1). The TK-80 can be
switched to the TCXO by removing resistors R682 and R683.
2-2. LO1 (PLL loop)
Q531, Q533, and Q535 are VCOs.
Q531 (VCO1) generates a signal of 73.145 to 83.544MHz.
Q533 (VCO2) generates a signal of 83.545 to 94.544MHz.
Q535 (VCO3) generates a signal of 94.545 to 103.045MHz.
The 20MHz reference signal of f
STD
is input to pin 15 of
IC502 and is divided by 40 to produce a 500kHz comparison
frequency. The output signal from the VCO is mixed with a
53.545 to 54.045MHz signal from the PLL (described later)
and IC503 (Mixer) to produce a 19.5 to 49.5MHz signal. It is
then input to pin 6 of IC502, divided, and compared with the
500kHz signal by the phase comparator. The VCO frequency
is then locked. The divide ratio date is supplied by the digital
unit.
At IC500, a 1.195 to 1.695MHz digital signal is generated
and the CP500, CP501 ladder resistor and Q522 D/A con-
verter are used to convert it into an analog signal. That signal
is put through a low-pass filter and mixed with 10MHz at
mixer IC504 to produce 8.305 to 8.805MHz.
Furthermore, 62.35MHz oscillated by X502 and Q517 is
mixed at mixer IC505 to become the above mentioned
53.545 to 54.045MHz signal.
Fig. 1
Frequency configuration
Summary of Contents for TK-80
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Page 83: ...TK 80 76 INTERCONNECTION DIAGRAM ...
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