TK-2310R
14
3-2. Driver and Final Amplifier Circuit
The signal from the T/R switch (D18 is on) is amplified by
the RF AMP (Q201) and pre-drive amplifier (Q203) to 50mW.
The output of the pre-drive amplifier is amplified by the
drive amplifier (Q204) and the RF final amplifier (Q205) to
5.0W (1W when the power is low).
The drive amplifier and the RF final amplifier consist of
two MOS FET stages.
The output of the RF final amplifier is then passed
through the antenna switch (D201 and D202) and the har-
monic filter (LPF), and is applied to the antenna terminal.
3-3. APC Circuit
The APC circuit always monitors the current flowing
through the drive amplifier (Q204) and the RF power ampli-
fier (Q205) and keeps a constant current. The voltage drop
at R307, R309 and R310 is caused by the current flowing
through the RF final amplifier. This voltage is applied to the
differential amplifier IC301 (1/2).
IC301 (2/2) compares the output voltage of IC301 (1/2)
with the reference voltage from IC811. The output of IC301
(2/2) controls the VG of the RF power amplifier and the drive
amplifier to make both voltages the same.
The change of power high/low is carried out by the
change of the reference voltage.
CIRCUIT DESCRIPTION
Fig. 5 Driver and final amplifier and APC circuit
4. Frequency Synthesizer Unit
4-1. Frequency synthesizer
The frequency synthesizer consists of the TCXO (X1),
VCO, PLL-IC (IC1), and buffer amplifiers.
The TCXO generates 16.8MHz. The frequency stability is
1.5ppm within the temperature range of –30°C to +60°C. The
frequency tuning and modulation of the TCXO are done to
apply voltage to pin 1 of the TCXO. The output of the TCXO
is applied to pin 10 of PLL-IC.
The VCO consists of 2 VCO and covers a dual range of
245~245.9875MHz and 294.95~295.9375MHz. The VCO
generates 294.95~295.9375MHz for providing the first local
signal for reception. The operating frequency is generated
by Q5 in transmitting mode and Q4 in receiving mode. The
oscillation frequency is controlled by applying the VCO con
-
trol voltage, obtained from the phase comparator (IC1) to
the variable capacitance diodes (D6 and D9 in transmitting
mode and D7, D10 and D12 in receiving mode)
The TX/RX pin of IC820 goes “high” in transmitting mode,
causing Q7 and Q4 to turn off, and Q5 turn on. The TX/RX
pin goes “low” in receiving mode.
The output from Q4 and Q5 are amplified by a buffer am-
plifier (Q8) and Q2, and then sent to the PLL-IC.
The PLL-IC consists of a prescaler, reference divider,
phase comparator, and charge pump. The input signal from
pin 10 and 17 of the PLL-IC is divided down and compared
at the phase comparator. The pulsed output signal of the
phase comparator is applied to the charge pump and trans-
formed into a DC signal in the loop filter (LPF). The DC sig-
nal is applied to the CV of the VCO and locked to keep the
VCO frequency constant.
PLL data is output from PL_STB (pin 20), PL_CLK (pin 8),
and PL_DAT (pin 21) of the MCU (IC820). The data is input
to the PLL-IC when the channel is changed or transmission
is changed to reception and vice versa. PLL lock condition is
always monitored by pin 18 (PL_UL) of the MCU. When the
PLL is unlocked, PL_UL goes low.
ANT
RF FINAL
AMP
ANT
SW
LPF
From
T/R SW
(D18)
D201,202
+B
PC/BPF2
(IC811)
RF
AMP
Q201
Q205
DRIVE
AMP
Q204
VDD
VG
Pre-DRIVE
AMP
Q203
IC301
(1/2)
IC301
(2/2)
R307
R309
R310
