KDC-MP6090R/MP7018/MP8017
14
CIRCUIT DESCRIPTION (MP3)
• Init Mode
“PLAY” and “MUTE” changes are ignored in this mode.
The internal state of the decoder will be updated only when
the decoder changes from the state “init” to the state
“decode”. The “init” phase ends when the first decoded
samples are at the output stage of the device.
• Decode Mode
This mode is completely described by the following table.
PLAY MUTE
Ciook State
PCM Output
Decoding
0
0
Not Running
0
No
0
1
Running
0
No
1
0
Runnig
Decoded Samples
Yes
1
1
Running
0
Yes
■
I
2
C BUS SPECIFCATION
The STA013 supports the I
2
C protocol. This protocol
defines any device that sends data on to the bus as a
transmitter and any device that reads the data as a receiv-
er. The device that controls the data transfer is known as
the master and the others as the slave. The master always
starts the transfer and provides the serial clock for syn-
chronisation. The STA013 is always a slave device in all its
communications.
●
COMMUNICATION PROTOCOL
• Data transition or change
Data changes on the SDA line must only occur when the
SCL clock is low. SDA transition while the clock is high are
used to identify START or STOP condition.
• Start condition
START is identified by a high to low transition of the data
bus SDA signal while the clock signal SCL is stable in the
high state.
A START condition must precede any command for data
transfer.
• Stop condition
STOP is identified by low to high transition of the data bus
SDA signal while the clock signal SCL is stable in the high
state. A STOP condition terminates communications
between STA013 and the bus master.
• Acknowledge bit
An acknowledge bit is used to indicate a sucoessful data
transfer. The bus transmitter, either master or slave,
releases the SDA bus after sending 8 bit of data.
During the 9th clock pulse the receiver pulls the SDA bus
low to acknowledge the receipt of 8 bits of data.
• Data input
During the data input the STA013 samples the SDA signal
on the rising edge of the ciock SCL.
For correct device operation the SDA signal has to be sta-
ble during the risng edge of the clock and the data can
change only when the SCL line is low.
●
DEVICE ADDRESSING
To start communication between the master and the
STA013, the master must initiate with a start condition.
Following this, the master sends onto the SDA line 8 bits
(MSB first) corresponding to the device select address and
read or write mode.
The 7 most significant bits are the device address identifi-
er, corresponding to the I
2
C bus definition. For the STA013
these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation RW, this bit
is set to 1 in read mode and 0 for write mode. After a
START condition the STA013 identifies on the bus the
device address and, if a match is found, it acknowledges
the identification on SDA bus during the 9th bit time. The
following byte after the device identification byte is the
internal space address.
●
WRITE OPERATION (see Fig. 7)
Following a START condition the master sends a device
select code with the RW bit set to 0.
The STA013 acknowledges this and waits for the byte of
internal address.
After receiving the internal bytes address the STA013
again responds with an acknowledge.
• Byte write
In the byte write mode the master sends one data byte,
this is acknowledged by STA013. The master then termi-
nates the transfer by generating a STOP condition.
• Multibyte write
The multibyte write mode can start from any internal
address. The transfer is terminated by the master gener-
atinga STOP condition.
DEV-ADDR
SUB-ADDR
DATA IN
RW
STOP
ACK
ACK
ACK
START
BYTE
WRITE
DEV-ADDR
SUB-ADDR
DATA IN
RW
STOP
ACK
ACK
ACK
DATA IN
ACK
START
MULTIBYTE
WRITE
Fig. 7 Write Mode Sequence
