19
DDX7032/7032M/712
DNX7120/7220/7320
Pin No.
Pin Name
I/O
Application
True Value
Table
Processing Operation Description
A14
IPOD_POW (NC)
O
Authentication chip power supply control (Not used)
A15
#WAIT
I
WAIT input (Not used)
A16
USB2_NEG
I/O USB2 data (Not used)
A17
NC
I
B1
AD25
O
Address bus
B2
#CS2
I
Watchdog startup
q
B2
#CS2
O
SRAM chip select
B3
#CS6
I
BOOT bus width select
w
B3
#CS6
O
Nor Flash chip select
B4
AD20
O
Address bus
B5
DA30
I/O Data bus
B6
AD18
O
Address bus
B7
EP_STBY
O
Permission to turn OFF the mother power supply
B8
AD17
O
Address bus
B9
RXCLK
I
(ETHER I/F for design)
B10
MIIRXD1
I
(ETHER I/F for design)
B11
MIITXD2
O
(ETHER I/F for design)
B12
TXEN
O
(ETHER I/F for design)
B13,14
NC
B15
USB2_POS
I/O USB2 data (Not used)
B16
DA_MCLK
O
AUDIO DAC Master clock
I2S
B17
3.3V
C1
AD23
O
Address bus
C2
DA26
I/O Data bus
C3
#CS3
O
SRAM chip select
C4
DA25
I/O Data bus
C5
AD24
O
Address bus
C6
AD19
O
Address bus
C7
EP_SREQ
O
EP9307 communication request
C8
#WR
O
Memory write
C9
MDIO
I/O (ETHER I/F for design)
C10
MIIRXD2
I
(ETHER I/F for design)
C11
TXCLK
I
(ETHER I/F for design)
C12
MIITXD0
O
(ETHER I/F for design)
C13
CLD
I
(ETHER I/F for design)
C14
NC
C15
TRSTN
I
(JTAG I/F for design)
C16,17
NC
D1
#SDCS3
O
SDRAM chip select
D2
DA23
I/O Data bus
D3
SDCLK
O
SDRAM clock
Commercial product: 100MHz
Thermal expansion product: 92MHz
D4
DA24
I/O Data bus
D5
NC
MICROCOMPUTER’S TERMINAL DESCRIPTION
