Keithley KPCMCIA-12AIAOH, User Manual

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KPCMCIA-12AIAOH User’s Manual I/O Registers C-17
Timer/counter port (base + 10, base + 11)
The timer/counter port can be accessed either as a 16-bit word at base + 8 or two consecutive
bytes at base + 8 (low byte) and base + 9 (high byte). The port contains a 16-bit reload register, a
16-bit up-counter, a 16-bit read latch register, and the associated control logic.
The reload register is write only. It holds the initial value (or the reload value) for the up-counter.
Each time the counter overflows, the next clock rising edge reloads the counter with this value.
The same value is also loaded into the counter as its initial value in mode 0. (See the discussion
below.)
The read latch register is read only. It holds the current count of the up-counter when a latch com-
mand is received. The content of this register will not change until the next latch command comes.
Refer to “Latch timer/counter command” to send the read latch command.
The up-counter cannot be accessed directly. It reloads on the next rising edge of the selected clock
from the reload register either when it reaches its final count of 65535 (hexadecimal FFFF) or
when the timer/counter is in mode 0.
Timer/counter operation modes
Bits 3 and 4 in the auxiliary control register (base + 15, write) determine the timer modes as sum-
marized in Table C-17.
Mode 0 is used to reload the up-counter. Note that the reloading only takes place when the next
rising edge of the selected clock source comes. For the internal clock source, it takes at least 1µs.
When the timer/counter is used to count external pulses, select mode 0 and the internal clock
source to guarantee the initial reloading by the internal clock and then switch the source to exter-
nal. Refer to “Timer/counter clock source” for information on setting the internal clock.
Mode 1 is designed to temporarily pause the up-counter. The up-counter is frozen in this mode.
Mode 2 is also named the “go” mode. The up-counter either starts or continues counting up on
the rising edge of the selected clock source. If the up-counter reaches its final count, it reloads
on the next clock rising edge.
In mode 3, the up-counter operation is controlled by the external gate signal [pin 18 on the PC
card 33-pin connector (pin 8 on the D-37)]. The counter “goes” when the signal is high (logic 1)
and stops when the signal is low (logic 0).
Table C-17
Timer/counter mode
Bit 4,3 Mode Timer/counter operation
00 0 Stop and reload the up-counter from the reload register
01 1 Pause
10 2 Start/Continue
11 3 Operation controlled by the gate input:
Gate = Low: Pause, Gate = High: Start/Continue