Keithley KPCMCIA-12AIAOH, User Manual

Page: 51 / 58

C-16 I/O Registers KPCMCIA-12AIAOH User’s Manual
The data word written into the D/A port is first latched into the 16-bit buffer register. It is then
loaded into the 16-bit shift register and shifted into the D/A channel’s input register across the
serial link. Bit 5 in the auxiliary status register is set to 1 to show that the buffer is occupied as
soon as the buffer register is written. It remains 1 until its content is loaded into the shift register.
By then, the bit is cleared to indicate that the buffer is empty.
Since the serial link needs 16 of the 2MHz clock cycles to complete one 16-bit data word, it takes
about 8µs for each data word transfer. The buffer register is only loaded into the shift register
when the latter has finished shifting. You must check this bit and make sure the buffer register is
empty before writing into it. Otherwise, the original data in the buffer register may become cor-
rupted. The interface hardware will neither prevent it from happening nor report it as an error.
D/A update modes
Depending on the D/A update mode, the data word shifted into the D/A channel may either be
passed immediately into the output register (direct update mode) or loaded into the output register
upon receiving the synchronous event (synchronous update modes).
Bits 1 and 0 of the auxiliary control register (base + 15, write) defines the D/A update modes as
summarized in Table C-16.
In mode 0, the D/A converter’s output register is updated as soon as the data word shifts into its
shift register, bypassing its input register, after the D/A port buffer register is written. There is no
synchronization between the two D/A channels in this mode. Each are operated independently.
In modes 1, 2, and 3 (the synchronous modes), the data word written into the port buffer register
is loaded into the D/A channel’s input register before it can be written into its output register.
Upon receiving a synchronous event, the output registers in both D/A channels are updated at the
same time.
In mode 1, the synchronous event is the timer overflow. The synchronous event in mode 2 is the
gate control going from low to high. In mode 3, the event is the pacer clock.
Table C-16
D/A update modes
Bit 1,0 Mode Update
00 0 Direct update immediately after the data word is written
01 1 Each time when the timer overflows
10 2 Each time when the gate control goes from low to high
11 3 Each time the A/D pacer clock fires