List of Illustrations
iii
3
Installation
Figure 3-1
Pin assignments for I/O connectors (J102 through J105) ............................................................................ 3-5
Figure 3-2
Connector locations and port group assignments ........................................................................................ 3-6
Figure 3-3
Using manufactured cables and accessories ................................................................................................ 3-8
Figure 3-4
Contact-closure monitoring at a KPCI-PIO96 board input system connections ....................................... 3-10
Figure 3-5
De-bounce circuit for an input of a KPCI-PIO96 board ............................................................................ 3-10
Figure 3-6
NPN transistor relay control for an output of a KPCI-PIO96 board.......................................................... 3-11
5
Troubleshooting
Figure 5-1
Problem isolation flowchart ......................................................................................................................... 5-4
Figure 5-2
Mating connector wiring for loop-back test............................................................................................... 5-11
Figure 5-3
IO Control Panel example.......................................................................................................................... 5-13
Figure 5-4
Setting port input and output ‘Configure’ switches ................................................................................... 5-14
Figure 5-5
Port A ‘write/read’ switch setting .............................................................................................................. 5-14
Figure 5-6
Port A output settings, bit pattern .............................................................................................................. 5-15
Figure 5-7
Port A output settings, bit pattern2 ............................................................................................................ 5-15
Figure 5-8
Correct bit patterns when port A is set to bit pattern 2. ............................................................................. 5-16
Figure 5-9
PIO Control Panel example........................................................................................................................ 5-18
Figure 5-10
Setting port ‘Configure’ switches .............................................................................................................. 5-19
Figure 5-11
Port ‘write/read’ switch settings ................................................................................................................ 5-19
Figure 5-12
Port output settings, bit pattern 1 ............................................................................................................... 5-20
Figure 5-13
Port output settings, bit pattern 2 ............................................................................................................... 5-21
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