Keithley KPCI-PDISO8A, User Manual

Page: 35 / 72

4-4 External Interrupts KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual
Refer to Table 4-2 for a list of external-interrupt responses.
For an additional application illustration, refer to the “ Interrupt example scenario ” subsection in
Appendix B . For information on setting and configuration of external interrupts, refer to your
DriverLINX software manuals.
NOTE
Do not confuse the external interrupt INT_REQ with the internal PCI
bus interrupt INTA, even though INT_REQ and INTA are linked by
hardware.
Table 4-2
External-interrupt responses
Result
Interrupt Control/Status
Register
Interrupt Control Bits
(x = don’t care)
Port Group
Control Register
(x = don’t care)
External Inputs at
J101
Interrupt Control/
Status Register
Status after Edge
Transition*
INT Enable
Bit 12
Polarity
Bit 6 Bit 6 Bit 5
Enable
Pins
3.21
Edge
Pins
4,22
Pending Bit
Bit 17
PCI-INT; No Latch 1 0 x 0 0
↑
1
PCI-INT; No Latch 1 1 x 0 0
↓
1
No PCI-INT; No Latch
(Programmed I/O Mode) 0 x x 0 0
↑
or
↓
0
No PCI-INT; Latch Input
Data 0 x 0 1 0
↑
1
No PCI-INT; No Latch 0 x 0 1 0
↓
0
No PCI-INT; No Latch 0 x 1 1 0
↑
0
No PCI-INT; Latch Input
Data 0 x 1 1 0
↓
1
No PCI-INT; No Latch
(Programmed I/O Mode) x x x x 1
↑
or
↓
0
PCI-INT; Latch Input Data 1 0 0 1 0
↑
1
No PCI-INT; Latch Input
Data 1 1 0 1 0
↑
1
No PCI-INT; No Latch 1 0 0 1 0
↓
0
PCI-INT; No Latch 1 1 0 1 0
↓
1
PCI-INT; No Latch 1 0 1 1 0
↑
1
No PCI-INT; No Latch 1 1 1 1 0
↑
0
No PCI-INT; Latch Input
Data 1 0 1 1 0
↓
1
PCI-INT; Latch Input Data 1 1 1 1 0
↓
1
*For bit 17, assume an initial clear state before edge.