![background image](http://html1.mh-extra.com/html/keithley/7001/7001_instruction-manual_4021029125.webp)
5-6
Figure 5-5
Model 7001 status register structure
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Trigger
Condition
Register
In Trigger Layer 1
(Always Zero)
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Trigger
Transition
Filter
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Trigger
Event
Register
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Trigger
Event
Enable
Register
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
OR
0
2
3
4
5
6
7
8
10
11
12
13
14
15
Questionable
Condition
Register
(Always Zero)
0
2
3
4
5
6
7
8
10
11
12
13
14
15
Questionable
Transition
Filter
0
2
3
4
5
6
7
8
10
11
12
13
14
15
Questionable
Event
Register
0
1111
2
3
4
5
6
7
8
10
11
12
13
14
15
Questionable
Event
Enable
Register
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
OR
0
Set
2
3
4
Trig
Arm
7
8
9
Idle
11
12
13
14
15
Operation
Condition
Register
(Always Zero)
0
Set
2
3
4
7
8
9
Idle
11
12
13
15
Operation
Transition
Filter
0
Set
2
3
4
7
8
9
Idle
11
12
13
15
Operation
Event
Register
0
Set
2
3
4
7
8
9
Idle
11
12
13
15
Operation
Event
Enable
Register
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
OR
14
14
14
Settling
Waiting in Trigger Layer
Waiting in an Arm Layer
Idle
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Arm
Condition
Register
In an Arm Layer
(Always Zero)
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Arm
Transition
Filter
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Arm
Event
Register
0
Seq 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Arm
Event
Enable
Register
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
OR
0
EAV
QSB
MAV
ESB
RQS/MSS
OSB
Status
Byte
Register
0
1
EAV
QSB
MAV
ESB
6
OSB
Service
Request
Enable
Register
&
&
&
&
&
&
&
Logical
OR
*STB?
*SRE
*SRE?
Master Summary Status (MSS)
EAV = Error Available
QSB = Questionable Summary Bit
MAV = Message Available
ESB = Event Summary Bit
RQS/MSS = Request for Service/Master Summary Staus
OSB = Operation Summary Bit
0
Lay 1
Lay 2
3
4
5
6
7
8
9
10
11
12
13
15
Sequence
Condition
Register
(Always Zero)
0
3
4
5
6
7
8
9
10
11
12
13
15
Sequence
Transition
Filter
0
3
4
5
6
7
8
9
10
11
12
13
15
Sequence
Event
Register
0
3
4
5
6
7
8
9
10
11
12
13
15
Sequence
Event
Enable
Register
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
OR
14
In Arm Layer 1
Lay 1
Lay 2
Lay 1
Lay 2
Lay 1
Lay 2
14
14
14
In Arm Layer 2
Error Queue
Output Queue
Trig
Trig
Trig
Arm
Arm
Arm
Note
: RQS bit is in serial poll byte,
MSS bit is in *STB? response.
1
14
14
OPC
RQC
QYE
DDE
EXE
CME
URQ
PON
8
9
8
11
12
13
15
Standard
Event
Status
Register
8
9
8
11
12
13
15
Standard
Event
Status
Enable
Register
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
OR
(Always Zero)
Operation Complete
Request Control
Query Error
Device Specific Error
Execution Error
Command Error
User Request
Power On
OPC
RQC
QYE
DDE
EXE
CME
URQ
PON
*ESR?
*ESE
*ESE?
0
9
9
9
9
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Summary of Contents for 7001
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