In this appendix:
Overview .................................................................................. B-1
Clearing registers and queues .................................................. B-3
Programming enable registers ................................................. B-3
Reading registers ..................................................................... B-3
Status byte and service request (SRQ) .................................... B-4
Status register sets ................................................................... B-8
Status reporting command summary ...................................... B-10
Overview
The Model 2110 provides a series of status registers and queues, allowing the operator to monitor
and manipulate the various instrument events. The status structure is shown in following figure. The
heart of the status structure is the Status Byte Register. This register can be read by the user's test
program to determine if a service request (SRQ) has occurred, and what event caused it.
Status byte and SRQ
The Status Byte Register receives the summary bits of the status register sets, queue, and buffer.
The registers monitor the various instrument events. When an enabled event occurs, it sets a
summary bit in the Status Byte Register. When a summary bit of the Status Byte and its
corresponding enable bit are set (as programmed by the user), the Request Service (RQS) bit will set
to indicate that a service request (SRQ) has occurred.
Status register sets
A typical status register set is made up of an event register and an event enable register.
The event enable register:
•
Accepts both read and write operations
•
Indicates bits in the corresponding event register that are ORed together to produce the summary
bit of the event register.
When an event occurs, the appropriate event register bit sets to 1. The bit remains latched to 1 until
the register is reset. When an event register bit and its corresponding enable bit are set (as
programmed by the user), the output (summary) of the register will set to 1, which then sets the
summary bit of the Status Byte Register.
Appendix B
Status model
