22
Time
Operation
start
Trigger
Data
1st Trigger Event Occurs
N samples
N samples
2nd Trigger Event Occurs
Figure 3-8: Re-Trigger Mode Acquisition
3�5 ADC Timing Control
3�5�1 Timebase
Timebase
Clock
Mux
SSI
Bus
[0]
SSI_TIMEBASE
SSI
Bus
[0
]
SSI_TIMEBASE
Onboard
Oscillator
10M
ADC0_CLK
ADC1_CLK
FPGA_MCLK
1-to-4
Clock
Buffer
&
PLL
SYNC_CLK
Figure 3-9: Timebase Architecture
An onboard timebase clock drives the sigma-delta ADC, with frequency exceeding the
sample rate and produced by a PLL chip, with output frequency programmable to superior
resolution. The PCIe- 69529 accepts the external timebase from SSI Bus Number 0 for
synchronization between modules.
3�5�2 DDS Timing vs� ADC
Sampling Rate
8k – 54kS/s
54k - 108kS/s
108 k – 192kS/s
DDS(PLL) CLK
6.144 M-41.472 MHz 13.824 M-27.648 MHz 20.736 M-36.864 MHz
Table 3-5: Timing Relationship between ADC and PLL Clock
3�5�3 Filter Delay in ADC
Filter delay indicates time required for data propagation through a converter. Both AI
channels experience filter delay due to filter circuitry and converter architecture, as
shown.
Summary of Contents for PCIe-69529
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