JYTEK PCIe-69529 User Manual Download Page 10

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Total Harmonic Distortion plus noise (THD+N)

THD+N (dBc)

Input Range (V)

54 kS/s
20 Hz to 22 kHz

108 kS/s
20 Hz to 45 kHz

192 kS/s
20 Hz to 42 kHz

±1V

-96

-94

-95

±10V

-96

-92

-95

1. 1 kHz input tone and -1 dBFS input amplitude

Intermodulation Distortion

IMD (dBc)

1,2

Input Range (V)

Fs = 54 kS/s

Fs = 108 kS/s

Fs = 192 kS/s

±1V

-103

-99

±10V

-105

-101

1. CCIF 14 kHz + 15 kHz
2. -6 dBFS input amplitude for each tone

Crosstalk

Crosstalk (dBc)

1,2

Input Range (V)

1 kHz

0.5 Fs

±1V, ±10V

-100

-97

1. Shorted input
2. -1 dBFS input amplitude

Interchannel Gain Mismatch

Input Range (V)

Gain Mismatch (dB)

±1V, ±10V

0.1

1. 1 kHz input tone and -1 dBFS input amplitude

Interchannel Phase Mismatch

Input Range (V)

Phase Mismatch (°)

±1V, ±10V

1 khz

20 khz

86.4 khz

0.1

0.442

1.64

1. -1 dBFS input amplitude

Summary of Contents for PCIe-69529

Page 1: ...PCIe 69529 8 CH 24 Bit 204 8 kS s Dynamic Signal Acquisition Module User s Manual Manual Rev 1 00 Revision Date Jul 16 2016...

Page 2: ...ent minor physical injury component damage data loss and or program corruption when trying to complete a task Informationtopreventseriousphysicalinjury componentdamage dataloss and or program corrupti...

Page 3: ...ions 14 3 1 Functional Block Diagram 14 3 2 Analog Input Channel 14 3 2 1 Analog Input Front End Configuration 14 3 2 2 Input Range and Data Format 15 3 2 3 ADC and Analog Input Filter 16 3 2 4 DMA Da...

Page 4: ...III...

Page 5: ...Input Range and Data Format 15 Table 3 2 Input Range Midscale Values 16 Table 3 3 ADC Sample Rates vs DDS Output Clock 16 Table 3 4 Preferred Characteristics for Analog Triggers 20 Table 3 5 Timing R...

Page 6: ...7 Figure 1 6 PCIe 69529 Side View 9 Figure 1 7 PCIe 69529 I O Array 10 Figure 3 1 Analog Input Architecture 14 Figure 3 2 Linked List of PCI Address DMA Descriptors 17 Figure 3 3 Trigger Architecture...

Page 7: ...EPE signal conditioning for accelerometers and microphones The PCIe 69529 is auto calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors Following auto calib...

Page 8: ...ts for 8KS s Fs 54kS s Over voltage protection Differential 42 4V Pseudo differential positive terminal 42 4 V negative terminal unprotected rated at 2 5 V Input impedance 1M 50 between negative input...

Page 9: ...kS s Fs 108 kS s Fs 192 kS s 1V 10V 104 104 105 1 1 kHz input tone and 1 dBFS input amplitude 2 Measurement Includes harmonics Dynamic Range Dynamic Range dBFS 1 Input Range V Fs 54 kS s Fs 108 kS s F...

Page 10: ...kS s Fs 108 kS s Fs 192 kS s 1V 103 99 99 10V 105 101 101 1 CCIF 14 kHz 15 kHz 2 6 dBFS input amplitude for each tone Crosstalk Crosstalk dBc 1 2 Input Range V 1 kHz 0 5 Fs 1V 10V 100 97 1 Shorted in...

Page 11: ...sponse Frequency Hz Magnitude dB Figure 1 1 Analog Input Channel Bandwidth 1dBFS 108kS s 10 1 10 0 10 1 4 5 4 3 5 3 2 5 2 1 5 1 0 5 0 Frequency Hz Magnitude dB Response when AC coupling enabled Figure...

Page 12: ...V Input Range 1 dBFS and 1 kHz Sine Wave Input Figure 1 3 Spurious Free Dynamic Range 54kS s 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 x 10 4 160 140 120 100 80 60 40 20 0 Frequency Hz Magnitude dB SFDR 108 kS...

Page 13: ...FDR 192 kS s 1V Input Range 1 dBFS and 1 kHz Sine Wave Input Figure 1 5 Spurious Free Dynamic Range 192kS s 1 3 2 Timebase Sampling Clock Sampling Clock Timebase Internal onboard synthesizer 10 MHz ac...

Page 14: ...rigger polarity Rising or falling edge Pulse width 20 ns minimum Table 1 3 Digital Trigger Input 1 3 4 General Specifications Physical Physical dimensions 167 64W x 106 68H mm 6 53 x 4 16 in Bus Bus i...

Page 15: ...9 1 4 Schematics and I O All dimensions are in mm 100 36 59 05 176 42 Figure 1 6 PCIe 69529 Side View...

Page 16: ...10 The PCIe 69529 I O array is labeled to indicate connectivity as shown Figure 1 7 PCIe 69529 I O Array...

Page 17: ...ides the following software development kits NET driver for Windows compatible with various application environments such as C VB NET VC NET VB VC BCB and Delphi 1 5 2 DSA DASK DSA DASK includes devic...

Page 18: ...ewdriver Anti static wrist strap Antistatic mat JYTEK PCIe 69529 DSA modules are electrostatically sensitive and can be easily damaged by static electricity The module must be handled on a grounded an...

Page 19: ...crew and the bracket cover 4 Line up the PCI express digitizer with the PCI express slot on the backpanel Slowly push down on the top of the PCI express digitizer until its card edge connector is rest...

Page 20: ...JFET Buffer OPAMP 3 3V 5V 12V FPGA ADC Control Trigger Control Data Processing FIFO Interface PCIe Controller PCIe Gen1 x4 PCIe Gen1 x4 Slot ADC BUS SSI Bus 0 7 SSI_TIMEBASE 3 3V 5V 12V Quad 24bit AD...

Page 21: ...e input signals is to be rejected AC coupling enables a high pass R C filter through the input signal path The corner frequency 3dB is about 0 5Hz Input for IEPE For applications that require sensors...

Page 22: ...M to 36 864 MHz Table 3 3 ADC Sample Rates vs DDS Output Clock Filter Each channel has a two pole lowpass filter The filters limit bandwidth of the signal path and reject wideband noise 3 2 4 DMA Data...

Page 23: ...tor nodes circularly to achieve a multibuffered DMA A linked list comprising three DMA descriptors Each descriptor contains a PCI address PCI dual address a transfer size and the pointer to the next d...

Page 24: ...ires identification of trigger source The PCIe 69529 supports internal software trigger external digital trigger and SSI Bus Number 5 as well as analog trigger Software Trigger The software trigger ge...

Page 25: ...69529 analog trigger circuitry can be configured to monitor one analog input channel from which data is acquired Selection of an analog input channel as the analog trigger channel does not influence t...

Page 26: ...119 V 800001 9 99999881 V 0 999999881 V 800000 10 V 1 V Table 3 4 Preferred Characteristics for Analog Triggers Trigger Export The PCIe 69529 utilizes SSI Bus Number 5 to act as a System Synchronizati...

Page 27: ...the period of PCIe_CLK X 2 32 1 and minimum is the period of PCIe_CLK 8 ns Time Operation start Trigger Data Trigger Event Occurs Acquisition stop Begin to transfer data to system N samples Acquisiti...

Page 28: ...quency exceeding the sample rate and produced by a PLL chip with output frequency programmable to superior resolution The PCIe 69529 accepts the external timebase from SSI Bus Number 0 for synchroniza...

Page 29: ...bling The PCIe 69529 utilizes the SSI Bus 0 7 as a System Synchronization Interface SSI Dedicate routing of timebase clock and trigger signals onto the SSI Bus enables the PCIe 69529 to simplify synch...

Page 30: ...llows 3 6 1 SSI_TIMEBASE As output the SSI_TIMEBASE signal transmits the onboard ADC timebase through the SSI bus As input the PCIe 69529 accepts the SSI_TIMEBASE signal as the source of the timebase...

Page 31: ...et to hardware In the absence of user assignment the driver loads constants stored in bank 0 If constants from Bank 1 are to be loaded the preferred bank can be designated as boot bank by software Fol...

Page 32: ...power source settings Always install and operate equipment near an easily accessible electrical socket outlet Secure the power cord do not place any object on over the power cord Only install attach a...

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