JVC XV-421BK, Service Manual

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XV-521BK/523GD/525BK/421BK
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Programmable I/O pins.Input mode after reset.
8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA.
MSB of the 32-bit word is written first. The host also reads and writes the decoder
internal registers and local SDRAM via HDATA.
3.3-V supply voltage for I/O signals.
8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA.
MSB of the 32-bit word is written first. The host also reads and writes the decoder
internal registers and local SDRAM via HDATA.
Ground for core logic and I/O signals.
8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA.
MSB of the 32-bit word is written first. The host also reads and writes the decoder
internal registers and local SDRAM via HDATA.
2.5-V supply voltage for core logic.
Hardware reset. An external device asserts RESET(active LOW) to execute a decoder
hardware reset. To ensure proper initialization after power is stable,assert RESET for at
least 20 ms.
Ground for core logic and I/O signals.
Transfer not complate / data acknowledge. Active LOW to indicate host initiated transfer
is not complate.WAIT is asserted after the falling edge of CS and reasserted when
decoder is ready to complate transfer cycle. Open drain signal, must be pulled-up via
1kW to 3.3 volts. Driven high for 10 ns before tristate.
Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts.
Driven high for 10 ns before tristate.
3.3-V supply voltage for I/O signals.
No Connection
Ground for core logic and I/O signals.
No Connection
Programmable I/O pins. Input mode after reset
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Input mode after reset
Ground for core logic and I/O signals.
Programmable I/O pins. Input mode after reset
Programmable I/O pins. Output mode after reset
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Output mode after reset
Ground for core logic and I/O signals.
Programmable I/O pins. Output mode after reset
2.5-V supply voltage for core logic.
Programmable I/O pins. Output mode after reset
Ground for core logic and I/O signals.
I/O
I/O
-
I/O
-
I/O
-
I
-
O
O
-
O
-
O
I/O
-
I/O
-
I/O
I/O
-
I/O
-
I/O
-
I/O
-
Pin No.
Symbol
PIO0
HDATA0
HDATA1
HDATA2
VDD-3.3
HDATA3
VSS
HDATA4
HDATA5
HDATA6
HDATA7
VDD-2.5
RESET
VSS
WAIT/DTACK
INT
VDD-3.3
NC
VSS
NC
PIO11
PIO12
PIO13
PIO14
PIO15
PIO16
VDD-3.3
PIO17
VSS
PIO18
PIO19
PIO20
PIO21
PIO22
PIO23
VDD-3.3
PIO24
VSS
PIO25
VDD-2.5
PIO26
VSS
I/O
Function
ZIVA3-PE0 (IC501) : AV Decoder
ZIVA3-PEO (1/5)