JVC XL-SV302SL, Service Manual

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XL-SV320SL/SV305GD
XL-SV308BU
1-8
XL-SV320SL/305GD/308BU
ES3210 Pin description
Name Number I/O Definition
VDD 1, 31, 51 I Voltage supply for 3.3V.
RAS# 2 O DRAM row address strobe (active low).
DWE# 3 O DRAM write enable (active low).
DA[8:0] 12:4 O DRAM multiplexed row and column address bus.
DBUS[15:0] 28:13 I/O DRAM data bus.
RESET# 29 I System rest (active low).
VSS 30,50,80,100 I Ground.
YUV[7:0] 39:32 O Y is luminance, UV are chrominance data bus for screen video interface.
YUV[7:0] for 8-bit YUV mode.
VSYNC 40 I/O Vertical sync for screen video interface. programmable for rising or falling edge.
HSYNC 41 I/O Horizontal sync for screen video interface, programmable for rising or falling edge.
CPUCLK 42 I RISC and system clock input. CPUCLK is used only if SEL-PLL[1:0]=00.
PCLK2X 43 I/O Pixel clock; two times the actual pixel clock for screen video interface.
PCLK 44 I/O Pixel clock qualifier in for screen video interface.
AUX[7.0] 54,52,53,49:45 I/O Auxiliary control pins (AUX0 and AUX1 are open collectors).
LD[7:0] 62:55 I/O RISC interface data bus.
LWR# 63 O RISC interface write enable (active low).
LOE# 64 O RISC interface output enable (active low).
LCS[3,1,0]# 65,66,67 O RISC interface chip select (active low).
LA[17:0] 87:82, 79:68 O RISC interface address bus.
VPP 81 I Digital supply voltage for 5V.
ACLK 88 I/O Master clock for external audio DAC (8.192MHz, 11.2896MHz, 12.288MHz,16.9344MHz,
and 18.432MHz).
AOUT 89 O Dual-purpose pin. AOUT is the audio interface serial data output.
/SEL-PLLO I Pins SEL-PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK for the
ES3210: 00=bypass PLL.
01=54MHz PLL.
10=67.5MHz PLL.
11=81MHz PLL.
ATCLK 90 I/O Audio transmit bit clock.
ATFS/ 91 O Dual-purpose pin. ATFS is the audio interface transmit frame sync.
SEL-PLL I Pins SEL-PLL[1:0] select phase-lick loop(PLL) clock frequency CPUCLK for the
ES3210. See the SEL-PLL0 pin above for the sttings.
DOE# 92 O DRAM output enable (active low).
AIN 93 I Audio interface serial data input.
ARCLK 94 I Audio receive bit clock.
ARFS 95 I Audio interface receive frame sync.
TDMCLK 96 I TDM interface serial clock.
TDMDR 97 I TDM interface serial data receive.
TDMFS 98 I TDM interface frame sync.
CAS# 99 O DRAM column address strobe bank 0 (active low).