XL-SV320SL/305GD/308BU
1-15
Pin No.
Pin Name
I/O
Description
34
FRDR
O
1,0
Focus drive output.
35
DVss1
-
-
Digital GND.
36
TEST
I
Test normally, GND
37
TES1
I
Test normally, GND
38
VC
I
Center voltage input
39
FE
I
Focus error signal input
40
SE
I
Sled error signal input
41
TE
I
Tracking error signal input
42
CE
I
Center servo analog input
43
RFDC
I
RF signal input
44
ADIO
O
Analog
Test No. connected
45
AVss0
-
-
Analog GND
46
IGEN
I
Constant current input for operational amplifier
47
AV
DD
0
-
-
Analog power supply
48
ASYO
O
1,0
EFM full-swing output. (low=Vss, high=V
DD
)
49
ASYI
I
Asymmetry comparator voltage input
50
RFAC
I
EFM signal input
51
AVss1
-
-
Analog GND
52
CLTV
I
Multiplier VCO1 control voltage input
53
FILO
O
Analog
Master PLL filter output (slave=digital PLL)
54
FILI
I
Master PLL filter input
55
PCO
O
1,Z,0
Master PLL charge pump output
56
AV
DD
1
-
-
Analog power supply
57
BIAS
I
Asymmetry circuit constant current input
58
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
59
V16M
I/O
1,0
Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM PLL clock
input by switching with the command.
60
VPCO
O
1,Z,0
Wide-band EFM PLL change pump output
61
DV
DD
2
-
-
Digital power supply
62
ASYE
I
Asymmetry circuit on/off (low=off, high=on)
63
MD2
I
Digital Out on/off control (low=off, high=on)
64
DOUT
O
1,0
Digital Out output
65
LRCK
O
1,0
D/A interface. LR clock output. f=Fs
66
PCMD
O
1,0
D/A interface. Serial data output (two’s complement, MSB first)
67
BCK
O
1,0
D/A interface. Bit clock output
68
EMPH
O
1,0
Outputs a high signal when the playback disc has emphasis, and a low signal when
there is no emphasis.
69
XTSL
I
Crystal selection input. Low when the crystal is 16.9344MHz; high when it is
33.8688MHz.
70
DVss2
-
-
Digital GND
71
XTAI
I
Crystal oscillation circuit input. When the master clock is input externally, input it from
this pin.
72
XTAO
O
Crystal oscillation circuit output.
73
SOUT
O
1,0
Serial data output in servo block.
74
SOCK
O
1,0
Serial data readout clock output in servo block.
75
XOLT
O
1,0
Serial data latch output in servo block.
76
SQCO
O
1,0
Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.
77
SQCK
I
SQCO readout clock input.
78
SCSY
I
GRSCOR resynchronization input.
79
SBSO
O
1,0
Sub-Q P to W serial output.
80
EXCK
I
SBSO readout clock input.
Summary of Contents for XL-SV302SL
Page 7: ...XL SV320SL 305GD 308BU 1 7 Pin configuration U1 ES3210 Block diagram Pin configuration ...
Page 9: ...XL SV320SL 305GD 308BU 1 9 U4 ES3207 Block diagram Pin configuration ...
Page 13: ...XL SV320SL 305GD 308BU 1 13 U5 CXD3068Q CD DSP Block diagram ...
Page 29: ...XL SV320SL SV305GD XL SV308BU 2 2 XL SV320SL 305GD 308BU Wiring diagram ...
Page 30: ...XL SV320SL 305GD 308BU 2 3 Block diagram ...
Page 31: ...XL SV302SL 305GD 308BU Schematic Diagrams MIC AMP Power Key VFD Circuit 2 4 ...
Page 32: ...MPEG Circuit XL SV302SL 305GD 308BU 2 5 ...
Page 33: ...Servo Circuit XL SV302SL 305GD 308BU 2 6 ...
Page 34: ...Output Circuit XL SV302SL 305GD 308BU 2 7 ...
Page 35: ...D A Circuit XL SV302SL 305GD 308BU 2 8 ...
Page 36: ...Memory Circuit XL SV302SL 305GD 308BU 2 9 ...
Page 38: ...MPEG Servo and Output PCB XL SV302SL 305GD 308BU Top View 2 11 ...
Page 39: ...XL SV302SL 305GD 308BU MIC AMP Board 2 12 ...
Page 40: ...XL SV302SL 305GD 308BU Key and FLD Display Board 2 13 ...