2-25(No.YF133)
REG_4.9V_IC4901
REG_3.1V_IC4901
L4904
NQL38DK-100X
TL4914
T
C4902
10/6.3
OP_CS
L4901
NQR0129-002X
TL4915
T
C4935
10/10
C4926
1
µ
IRIS_PS
REG_3.1V
M_REG4.9
GND
REG_4.9V
IC4903
R1100D311C-X
1
Vout
2
VDD
3
GND
C4906
0.1
T
C4903
10/10
C4925
1
µ
R4932
GND
C4905
0.1
C4936
0.01
CAM_CLK
L4902
NQL38DK-100X
10
µ
1 N.C.
37 N.C.
2 N.C.
38 N.C.
66 N.C.
39 DVSS
4 DVDD(3V)
5 RETB
40 SCK
67 TEST0
86 TEST1
98 MONI0
87 TEST2
68 CS
41 SIN
6 CLK
7 VD
42 SOUT
69 PDWNB
8 HD
43 PLS1
9 PLS2
88 MODESEL
70 AVSS1
10
N.C.
44
AVDD1(3V)
11
DAC0
45
DAC1
12
DAC2
71
DAC3
46
DAC4
13
DAC5
14
DAC6
47
DAC7
72
DAC8
89
DAC9
99
N.C.
90
N.C.
73
N.C.
48
N
C
61
SENS
82
N.C.
95
N.C.
97
N.C.
96
LED1
83
LED2
62
N.C.
33
N.C.
34
C1
63
C_VCC
84
C_GND
35
C2
64
D2
36
D_GND
85
D_VCC
65
D1
IR_OUT
CAM_VD
L4903
NQL38DK-100X
10
µ
T
C4932
10/10
C4934
OPEN
HDIRS
R4925
R4931
270
CAM_OUT
R4944
CLK27_AT
CAM_IN
F/Z_RST
TL4901
TL4902
TL4903
IC4902
MM1614GN-X
1
Cont
2
GND
3
Noise
4
Vout
5
Vin
C4927
0.01
µ
C4923
1
µ
C4924
1u
ASPECT
R4993
(N2)
(W4)
(W2)
(W3)
(W1)
IC4901
JCY0223-X
Dch
Cch
100K
0
Ω
470
TO V I/O
TO P.PRCS
TO CDS/TG,P.PRCS
TO P.PRCS
TO CDS/TG,P.PRCS
TO P.PRCS
TO MAIN IF(CN103)
TO MAIN IF
MAIN(OP DRV) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
