2-19(No.YF133)
SDR_DQ28
SDR_DQ20
SDR_DQ26
SDR_DQ30
SDR_DQ19
SDR_DQ24
SDR_DQ22
SDR_DQ27
SDR_DQ25
SDR_DQ23
SDR_DQ29
SDR_DQ21
SDR_DQ18
SDR_DQ31
SDR_DQ17
SDR_DQ16
PMA1
PMD1
PMD13
XPMCS7
PMD2
PMA7
PMD12
PMA6
PMD15
PMA21
XPMOE
PMD6
PMA3
PMA16
PMA4
PMA5
PMD5
PMA11
PMA13
XPMWE
PMD9
PMD0
PMA17
PMD10
PMA10
PMA19
PMA8
PMD8
PMA18
PMD7
PMD11
PMA14
PMD14
PMD4
PMA15
PMA20
PMA12
PMA2
PMA9
PMD3
GND
REG_3.1V
L4301
NQR0129-002X
C4301
4.7
R4301
47k
L4302
OPEN
L4303
NQR0154-003X
T
C4304
OPEN
C4305
4.7
RA4301
100k
1
8
F880[2]
RA4301
100k
2
7
CF PORT POWERUP
RA4301
100k
3
6
CF PORT POWERUP
RA4302
100k
3
6
USB PORT POWERUP
RA4302
100k
1
8
CF PORT POWERUP
RA4302
100k
4
5
CF PORT POWERUP
RA4301
100k
4
5
CPU SELECT
RA4302
100k
2
7
F89E[6]
RA4304
100k
1
8
F89E[5:3]
RA4303
100k
4
5
F89E[5:3]
RA4303
100k
3
6
RESERVED
RA4303
100k
1
8
F89E[5:3]
RA4304
100k
3
6
MEMORY WIDTH FOR FLAS
01: 16bit
RA4303
100k
2
7
MEMORY WIDTH FOR FLAS
01: 16bit
RA4304
100k
4
5
F880[0]
RA4304
100k
2
7
F880[1]
FLSH_RST
IC4301
SP32J55BFI12D03
16
A16
15
BYTE
13
VSS
14
DQ15/A-1
35
DQ7
34
DQ14
12
DQ6
33
DQ13
46
DQ5
45
DQ12
11
DQ4
32
VCC
31
DQ11
10
DQ3
44
DQ10
43
DQ2
30
DQ9
9
DQ1
29
DQ8
28
DQ0
7
OE
8
VSS
6
CE
5
A0
4
A1
3
A2
1
A3
2
A4
27
A5
26
A6
24
A7
25
A17
41
A18
23
RY/BY
40
WP/ACC
48
NC
39
RESET
22
WE
42
A20
47
A19
38
A8
21
A9
37
A10
36
A11
19
A12
20
A13
18
A14
17
A15
C4302
0.1
C4352
1
IC4304
R1114N251B-X
1
VDD
2
GND
3
CE
4
NC
5
VOUT
C4351
1
SREG2.5V
[4M FLASH_MEMORY]
2.5V
C
VACANT NO.
4352
L
4303
R
4303
RA
4304
IC
4304
LAST NO.
4311-4350
TO SUB CPU,CDS/TG
TO MPEG2,V I/O
MAIN(DSP MEM) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.