2-13(No.YF076)
MAIN(VIDEO) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
MAIN(VIDEO)
1
0
DCO2
TL3201
REG_4.8V
R3206
L3203
NQR0006-001X
DCO1
DYO1
VC1
R3730
4.7k
CLK27A
DCO0
L3204
10u
L3201
NQR0129-002X
OSD_HD
VOI_CLK
DYO2
DOT_CLK
T_F_V_RST
ASPECT
C3206 0.01
VC0
R3201
100
R3210
DCO3
R3205
OPEN
T
C3204
10/6.3
VC3
R320
27k
VIF_CS
VOI_IN
R3207
OPEN
DYO3
T
C3201
10/6.3
ANA_IN_H
GND
T
C3205
10/6.3
CLK27B
REG_3.1V
OUTH
VOI_OUT
BLKB
PSCTL
REG_1.7V
L3202
NQR0129-002X
BLKA
C3207 0.01
C3202
1
BLKC
S_IN_L
C3203
1
VC2
S2_DET
R3208
820
DYO0
OUTV
OSD_VD
R3209
IC3201
JCP8055FP
1 HDCVF
2 VDCVF
3 CSYNC
4 VDOUT
5 SCANMODE
6 VDD(C)
7 VSS
8 RESVD
9 RESHD
10 SDOUT
11 SDIN
12 SCLK
13 CS
14 VDD(I)
15 VSS
16 RST
17
CLK
18
VC0
19
VC1
20
VC2
21
VC3
22
BLK1
23
BLK2
24
BLK3
25
HDOUT
26
VSS
27
VDD(I)
28
CLKOSD
29
AVSS
30
AVDD
31
IREF2
32
CROUT
33
ABAR2
34
COMP2
35
CBOUT
36
VREF2
37
COUT
38
AVDD
39
AVSS
40
IREF1
41
YCOUT
42
ABAR1
43
COMP1
44
YSOUT
45
VREF1
46
AVSS
47
AVDD
48
SCANEN
49
AMUTE
50
HRP1
51
HRP2
52
CSI0
53
CSI1
54
CSI2
55
CSI3
56
ADDATEST
57
VDD(C)
58
VSS
59
YSI0
60
YSI1
61
YSI2
62
YSI3
63
INH
64
INV
C3208
0.01
C3209
0.01
C3216
0.01
TL3202
TL3203
0
Ω
10
10
TO OP DRV
TO REG
TO PARAGON
TO CPU,
PARAGON
TO CPU
TO CPU,
OP DRV
TO CPU,
CDS/TG,
OP DRV
TO CPU,
PARAGON