2-11(No.YF076)
MAIN(PARAGON) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
ADIN6
OUTV
ADIN7
HDIN
ADIN8
ADIN8
REF_CLK
ADIN7
ADIN6
ADIN1
PBLK
ADIN5
ADIN0
ADIN4
ADIN9
HDIN
ADIN3
VDIN
ADIN2
CPOB
ADIN9
ID
CLKI
ADIN0 ADIN1 ADIN2
ID
CLKI
ADIN3
CPOB
F/Z_MCK
VD_F/Z
OSD_VD
ADIN4
PBLK
ADIN5
OUTH
VDIN
DYO0
DYO1
DYO2
DYO3
DCO0
DCO1
DCO2
DCO3
REC_CTL
REC_DATA
OMT
MFLD
MVD
XINT
SPA
TSR
FRP
CPU_WAIT
DSP_CS
CDAS
CDRE
CDWE
ADDT15
ADDT14
ADDT13
ADDT12
ADDT11
ADDT10
ADDT09
ADDT08
ADDT07
ADDT06
ADDT05
ADDT04
ADDT03
ADDT02
ADDT01
ADDT00
F/Z_MCK
HID
REC_CLK
DSP_RST
CLK27B
VD_F/Z HDIRS VDIRS
HDIRS
VDIRS
CLK27A
IRIS_MCK
IRIS_MCK
C3070
0.01
VD_F/Z
ADIN4
D3004
EC2C01C-TR-X
C3054 0.01
C3059
1
ADIN1
C3061
0.01
C3055 0.01
C3058 0.0047
ADIN6
R3034
56
HDIN
C3064
0.1
TL3002
R3061
OPEN
R3035
56
TL3006
C3062
0.01
R3031
10k
R3042
OPEN
C3052
0.1
F/Z_MCK
R3029
220k
TL3004
AD
ADA
AD
AD
ADV
AD
ADA
AD
ADV
AD
DAAO
DAA
DA
DAV
DAV
DAAO
DAA
DA
DAV
DAV
PLLA
PLL
LPF
LPF4
PLLA
PLL
PLLA
PLL
LPF
LPF24
PLLA
PLL
VC
PLLA
PLL
VC
PLLA
PLL
V
OS
OS
ADD
ADD_V
VCX
VCXO
ADD
VCX
VCXO
ADD_V
ADD
OS
OS
PWMA
A
A
AIL
AI
AO
ADD_V
ADD
ADD_V
ADD_V
ADD
ADD_V
ADD
ADD_V
140
ADIN11
43
ADIN10
141
ADIN9
44
ADIN8
142
ADIN7
45
ADIN6
143
ADIN5
46
ADIN4
144
ADIN3
47
ADIN2
146
ADIN1
49
ADIN0
28
AYO0
126
AYO1
296
AYO2
216
AYO3
29
AC00
127
ACO1
30
ACO2
299
ACO3
32
OUTHA
219
OUTVA
31
CLK27A
128
CLK27B
135
VDANA
298
ADD_VDDE
217
ADD_VSS
218
ADD_VDDL
129
PLLREF
300
PLLFB
131
ADD_VSS
34
ADD_VDDE
220
EXTDATA7
33
EXTDATA6
305
EXTDATA5
301
EXTDATA4
130
EXTDATA3
36
EXTDATA2
223
EXTDATA1
134
EXTDATA0
221
EXTACCESS
132
EXTREQ
35
EXTFRP
302
ADD_VDDE
303
ADD_VSS
304
VDDL
38
CLK54I
39
VDDP
136
VSSP
225
ADD_VDDL
40
ADD_VSS
306
ADD_VDDE
226
JTEST0
307
JTEST1
41
JTEST2
138
JTEST3
227
JTEST4
42
JTEST5
308
JTEST6
137
JTEST7
101
JTEST8
100
JTEST9
25
JTEST10
26
JTEST11
124
JTEST12
27
JTEST13
75
JTEST14
76
JTEST15
170
JTEST16
77
JTEST17
50
JTEST18
51
JTEST19
147
JTEST20
52
JTEST21
191
JTEST22
192
JTEST23
222
JTEST24
133
JTEST25
309
JTEST26
1
JTEST27
229
HDTG
310
VDTG
231
OBCP
232
ID
48
CLKI
233
PBLK
139
ADD_VSS
228
ADD_VDDE
313
VSS
230
ADD_VDDL
145
VSS
311 OJSEL
312 CCDSEL
234 TVSEL
314
PLLSEL
235 CLK27SEL
318 CPUBUSTYPE
236 VCC
2 VPD
20 PBI
148 PWR1
316 PWR2
53 PWR3
149 TTST
55 TBST
315 FRRES
237 VCC
54 ADD_VDDL
150 ADD_VSS
238 VCC
317 MTEST
56 TCK
239 TMS
152 TRST
240 TDI
57 TDO
153 VCC
320 ADD_VSS
319 ADD_VDDE
151 CLK24O
154 VCC
58 DSYO0
241 DSYO1
59 DSYO2
242 DSYO3
155 DSYO4
60 DSYO5
321 DSYO6
322 DSYO7
243 VCC
156 ADD_VSS
61 ADD_VDDE
244 DSCO0
157 DSCO1
324 DSCO2
323 DSCO3
62 DSCO4
245 DSCO5
158 DSCO6
63 DSCO7
64 ADD_VDDL
159 ADD_VSS
246 ADD_VDDE
65 DSYIO0
325 DSYIO1
328 DSYIO2
160 DSYIO3
247 DSYIO4
66 DSYIO5
161 DSYIO6
248 DSYIO7
327 ADD_VSS
67 ADD_VDDE
326 DSCIO0
162 DSCIO1
249 DSCIO2
68 DSCIO3
163 DSCIO4
250 DSCIO5
69 DSCIO6
329 DSCIO7
171 HDDSC
335 VDDSC
257 FLDDSC
78 CLKDSC
332 ADD_VDDE
164 ADD_VSS
252 ADD_VDDL
251 PHYAVS2
165 PHYAVD2
70 PHYTPB
71 PHYXTPB
166 PHYRO
330 PHYAVD3
253 PHYAVS3
331 PHYTPBIAS
72
PHYXTPA
167
PHYTPA
73
PHYAVD1
254
PHYAVS1
168
PHYVSA
333
PHYVDA
255
PHYFIL
74
PHYRF
169
PHYVSR
256
PHYVDR
172
ADD_VSS
334
VDDH
258
CLK4M5
79
CLK1M0
173
VDMDA
80
HDIRS
337
VDIRS
259
CLK27O
174
ADD_VDDE
336
VSS
81
BUS0
260
BUS1
175
BUS2
261
BUS3
82
BUS4
176
BUS5
339
BUS6
177
BUS7
84
BUS8
263
BUS9 BUS10
178
85
BUS11
341
BUS12
264
BUS13
179
BUS14
86
BUS15
83
ADD_VDDL
338
VSS
262
ADD_VDDE
340
VSS
186
WE
187
RE
95
AS
272
CS
342
CPUWAIT
268
CPUWAITLOGIC
269
SEPBUSCLK
182
ADD_VDDE
265
FRREF
180
TRKREF
343
SPA
184
HID
270
HSP
89
XINT
87
ADD_VSS
266
ADD_VDDL
88
HDCPU
267
VDCPU
90
FLDCPU
344
OMT
185
CLR
347
VSS
183
ADD_VDDE
181
PWM27O
91
OSC27O
346
VSS
92
OSC27I
345
ADD_VDDE
93
OSC4185O
271
ADD_VDDE
94
OSC4185I
348
VSS
351
ADD_VDDL
188
ADD_VDDE
273
ADD_VSS
96
CLK135O
189
PBCLKO
349
REFCLK
274
RECDATA
350
RECCLK
97
DISCRI
190
SBE
98
ADD_VSS
275
ADD_VDDE
99
ADD_VSS
276
ADD_VDDE
352
PBCLKI
193
RECCTL
R3040
2.4k
PBLK
CH
C3060
270p
R3038 5.1k
TL3001
CLKI
C3050 0.01
TL3007
CPOB
M_VCOCTL
C3069 0.01
ADIN8
C3057
0.01
ADIN3
ADIN7
FSPLLCTL
C3065
0.01
PBVCOCTL
C3049 0.01
R3037
56
C3066 0.01
R3033 3.9k
ADIN2
L3012
R3066
10k
R3036
56
R3030
10k
ID
C3068 0.01
TL3003
TL3005
ADIN0
C3067 0.01
VDIN
R3062
OPEN
ADIN9
ADIN5
C3053
1000p
C3051
47p
R3032
3.9k
C3056 0.01
C3063
0.01
TL3008
TL3009
TL3010
RA3003
10
1 2 3 4
8 7 6 5
RA3004
10
1 2 3 4
8 7 6 5
R3090
0
R3091
OPEN
0
Ω
0
Ω
R3075
0
Ω
NTSC
R3076 0
Ω
R3078
OPEN
PAL
R3085
10
R3089
1
0
RA3012
10k
4
2
1
3
5
7
8
6
R3051
100
R3045
0
Ω
C3076
OPEN
TPB-
TPB+
TPA-
TPA+
TL3012
GND
TL3015
R3069
OPEN
HDIRS
VDIRS
C3077 OPEN
TVSEL
R3077
OPEN
IRIS_MCK
IC3001
JCY0205
R3070
4
7
R3063
0
Ω
R3072
0
Ω
R3071
0
Ω
_0.5%
_0.5%
_0.5%
R3043
0
Ω
R3060
1k
R3068
0
Ω
_0.5%
2.2u
_0.5%
R3064
0
Ω
R3073
R3074
CPUWAITLOGIC
TVSEL SW
TO CPU
MAIN(PARAGON)
1
0
TO CDS/TG
TO CDS/TG
TO MAIN IF
(CN107,JACK)
TO OP DRV
TO OP DRV