A
1
2
3
4
5
B
C
D
R3231
R3232
R3218
R3233
R3234
R3210
R3239
L3205
C3208
R3235
R3236
R3237
R3238
MPGFLD
R3207
TL3204
IC3203
C3201
IC3204
R3209
C3241
C3240
BLKC
C3243
C3242
C3244
TL3203
REG_2.5V
IC3201
R3213
R3214
DV2CKOUT
R3215
R3216
L3203
L3204
C3204
C3205
L3201
L3202
C3202
C3203
REG_3.1V
GND
R3217
VI7
VI6
VI5
VI4
VI3
VI2
VI1
VI0
MPGVSYNC
MPGHSYNC
DV2OUT0
DV2OUT1
DV2OUT2
DV2OUT3
DV2OUT4
DV2OUT5
DV2OUT6
DV2OUT7
VIF_IN
VIF_OUT
VIF_CLK
VENC_CS
VENC_RST
VC3
VC2
VC1
VC0
BLKB
OSD_HD
OUTV2
OSD_VD
DOT_CLK
BLKA
R3201
IC3202
C3238
C3230
C3207
C3206
C3236
C3233
C3227
C3214
TL3202
C3234
C3211
C3213
C3209
/6.3
T
MM1612FN-X
T
MM1611JN-X
NC
NC
NC
NC
NC
RST
VSS
VSS
VSS
CS00
CS01
CS02
CS03
YS00
YS01
YS02
YS03
VDD(I/O)
OUTH
OUTV
OUTH2
OUTV2
ZCNT
SDOUT
VDD(CORE)
CLK
SDIN
SCLK
CS
VC0
VC1
VC2
VC3
BLK1
BLK2
BLK3
HDOUT
VDOUT
CLKOSD
HDCVF
VDCVF
VDD(C
VSS
VDD
C
SC
V
CB
CO
A
CR
I
VDD
VSS
VDD(1
VSS(1
V
YS
CO
A
YC
I
VSS
VDD
VDD
VSS
JCP8075
T
T
NQR0129-002X
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VDD(I/O)
CSYNC
SCANMODE
SCANEN
ADDATEST
VCC
IPTEST
VDD(I/O)
HRP1
HRP2
VDD(CORE)
WYSI0
WYSI1
WYSI2
WYSI3
MONI1
MONI2
VDD(CORE)
WCLK
WCSI0
WCSI1
WCSI2
WCSI3
WINV
WINH
SDR_ONH
VDD(I/O)
VDD(CORE)
RESVD
RESHD
AMUTE
SCANI1
SCANI2
VCCQ
VDD(I/O)
YSI7
YSI6
YSI5
YSI4
YSI3
YSI2
YSI1
YSI0
VSSQ
VSSQ
VCCQ
VDD(CORE)
VCC
VDD(I/O)
VDD(CORE)
INV
INH
CSI7
CSI6
CSI5
CSI4
CSI3
CSI2
CSI1
CSI0
VCCQ
VSSQ
VCCQ
VDD(I/O)
VDD(CORE)
VSSQ
0
0
47k
0
0
10
µ
10
0
0
0
0
0
10/6.3
0.01
1
0.01
1
1
0
0
0
0
Ω
0
0
0
1
OPEN
100
0.01
0.1
0.1
0.01
OPEN
0.01
0.01
0.01
0.1
0.1
0.1
0.1
TO CN203
TO CN203
TO CN203
LCD DRV
TO SUB CPU
TO REG
ANALOG(V I/O)
2
0
ANALOG(V I/O) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked (
) is not used.
2-23