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NJU26209 

- 8 - 

Ver.2008-12-04

 

Pin setting

 

 

The NJU26209 operates default command setting after resetting the NJU26209. In addition, the NJU26209 

restricts operation at power on by setting PROC pin and MUTEb pin. These pins are input pin. However, these pins 
operate as bi-directional pins. Connect with V

DDIO

 or V

SSIO

 through 3.3k

 resistance. 

 

Table 7   Pin setting 

Pin No. 

Symbol 

Setting 

Function 

“High” 

The NJU26209 operates default setting after reset. 

13 PROC 

“Low” 

The NJU26209 does not operate after reset. Sending start 
command is required for starting operation. 

“High” 

Master volume is set 0dB after reset. 

11 MUTEb 

“Low” 

Master volume is set mute after reset.   

 
 

 

WatchDog Clock

 

 
The NJU26209 outputs clock pulse through WDC (Pin No.12) during normal operation. The WDC clock is useful 

to check the status of the NJU26209 operation. For example, a microcomputer monitors the WDC clock and checks 
the status of the NJU26209. When the WDC clock pulse is lost or not normal clock cycle, the NJU26209 does not 
operate correctly. Then reset the NJU26209 and set up the NJU26209 again. The WDC clock is able to be variable 
for 0msec to 100msec by command. Default setting of WDC clock is 100msec. 

 
The WDC pin is open drain output. The WDC pin setting (Table 8) 

 

Table 8    WDC pin setting 

 
 
 

 
 

Note:

 The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing. 

In slave mode, when there is no input of BCKI/LRI, WDC can’t output. 
It is required to set up a sampling rate correctly. 

 

 
 
 
 

Pin No.  Symbol 

Setting 

WDC pin is used. 

Connect with V

DDIO

 through 3.3k

 resistance. 

12 WDC 

WDC pin is not used. 

Connect with V

SSIO

 through 3.3k

 resistance.   

Do not open WDC pin. 

Summary of Contents for NJU26209

Page 1: ...Control Bass Management TimeAlignment Master Volume Input Trim Channel Trim Hardware 24bit Fixed point Digital Signal Processing Maximum Clock Frequency 12 288MHz Standard built in PLLCircuit DigitalAudio Interface 4 Input ports 4 Output ports DigitalAudio Format I2 S 24bit left justified right justified BCK 32fs 64fs Master Slave Mode Microcomputer Interface I2 C Bus Standard mode 100kbps Fast mo...

Page 2: ...R ADDR ADDR ADDRESS ESS ESS ESS GENERATION GENERATION GENERATION GENERATION UNIT UNIT UNIT UNIT 24 24 24 24 BIT BIT BIT BIT x x x x 24 24 24 24 BIT BIT BIT BIT MULTIPLIER MULTIPLIER MULTIPLIER MULTIPLIER DSP DSP DSP DSP ARITHMETIC ARITHMETIC ARITHMETIC ARITHMETIC UNIT UNIT UNIT UNIT BCK BCK BCK BCKO O O O SERIAL SERIAL SERIAL SERIAL AUDIO AUDIO AUDIO AUDIO INTERFACE INTERFACE INTERFACE INTERFACE L...

Page 3: ... Trim Pro Logic II 5ch Input Trimmer Pro Logic II 3ch SDI0 SDO2 SDO1 SDI3 SDI2 SDI1 C SW L R LS RS Phantom Center Bass Management RS LS C LFE L R RS LS C L R CPLII RS LS C L R LM RM RS LS C L R LM RM RS LS C L R LM RM SW RS LS C L R LM RM SW SDO3 SDO0 DAEP Time Alignment Time Alignment Time Alignment Time Alignment Time Alignment ...

Page 4: ...6 7 8 9 10 11 12 VDD VSS VSSIO VDDIO SDO0 SDO1 SDO2 SDO3 SDI3 SDI2 SDI1 SDI0 LRI VDDIO BCKI VSS VDD TEST MUTEb WDC 13 14 15 16 PROC VSSIO VDDIO SEL 36 35 34 33 LRO BCKO MCK VDDIO 17 18 19 20 VDDPLL VSSPLL VSS VDD 21 22 CLKOUT CLK 32 31 30 29 SDA SDOUT SCL SCK AD2 SSb AD1 SDIN 28 27 26 25 TEST TEST TEST RESETb 24 23 VDDIO VSSIO ...

Page 5: ...upply 1 8V 21 CLKOUT O OSC Clock Output 22 CLK I OSC Clock Input 12 288MHz 23 VSSIO I O Power Supply GND 24 VDDIO I O Power Supply 3 3V 25 RESETb I Reset RESETb 0 DSP Reset 26 TEST I for test connect to VDDIO 27 TEST I for test connect to VSSIO 28 TEST I for test connect to VSSIO 29 AD1 SDIN I I 2 CAddress I 2 C mode Serial In 4 wire serial mode 30 AD2 SSb I I 2 CAddress I 2 C mode Serial enable 4...

Page 6: ...bus or 4 Wire serial bus Data transfers are in 8 bits packets 1 byte when using either format The SHI operates only in a SLAVE fashion Ahost controller connected to the interface always drives the clock SCL SCK line and initiates data transfers regardless of the chosen communication protocol The detail I2 C bus and 4 Wire Serial bus information are described in the NJU26200 Series Hardware Data Sh...

Page 7: ...e byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin Data transfers are MSB first and are enabled by setting SSb Low Data is clocked into SDIN on rising transitions of SCK Data is latched at SDOUT on falling transitions of SCK except for the first byte MSB which is latched on the falling transitions of SSb SDOUT is always CMOS output SDOUT does not ...

Page 8: ...ing normal operation The WDC clock is useful to check the status of the NJU26209 operation For example a microcomputer monitors the WDC clock and checks the status of the NJU26209 When the WDC clock pulse is lost or not normal clock cycle the NJU26209 does not operate correctly Then reset the NJU26209 and set up the NJU26209 again The WDC clock is able to be variable for 0msec to 100msec by comman...

Page 9: ... Bass Management Center Trim Command 14 Bass Management L R Trim Command 15 Bass Management LS RS Trim Command 16 Front Delay Control Command 17 Middle Delay Control Command 18 Surround Delay Control Command 19 Center Delay Control Command 20 Subwoofer Delay Control Command 21 PNG Mode Command 22 Firmware Version Number Request Command 23 DSP Reset Command 24 Start Command 25 Nop Command Notes In ...

Page 10: ...olby Laboratories Please refer to the licensing application manual issued by Dolby Laboratories CAUTION Thespecificationsonthisdatabookareonly givenforinformation withoutanyguarantee asregardseither mistakesoromissions The applicationcircuitsinthisdatabookare describedonlytoshowrepresentativeusages oftheproductandnotintendedforthe guaranteeorpermissionofanyrightincluding theindustrialrights ...

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