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Jorjin WG1300-B0, User Manual

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Jorjin WG1300-B0 User Manual Download Page 14

                                       

Doc No: WG1300BE00 EM Board-UG-R02 

 

                                                                                                                                                                           

Copyright 

©

 JORJIN TECHNOLOGIES INC. 2014 

http://WWW.JORJIN.COM.TW 

CONFIDENTIAL

 

Page 13 

2.4. 

 

Schematics 

Figure 4 is the schematics of WG1300E00 EM Board 
 

C7
NL_1uF

CAP1608

R16
NL_100K

RES1005

W

L_T

X

VBAT_SY S

R6
NL_0R

RES1005

To VIO_SYS Host Level

W

L_D

BG

VBAT_SY S

R19
NL_10K

RES1005

VBAT_SY S

U1

WG1300-B0

E_N51_14.5X14.5_1.3

W

L_U

AR

T

_D

BG

2

NS_UARTD

33

W

L_EN

1

4

W

L_EN

2

3

W

L_R

S232_T

X

5

W

L_R

S232_R

X

6

EXT_32K

17

GND

36

SC

L_C

C

3000

24

SC

L_EEPR

OM

23

SD

A_C

C

3000

26

SD

A_EEPR

OM

25

SPI_IRQ

13

SPI_DOUT

12

SPI_CS

15

SPI_CLK

14

SPI_DIN

11

RF_ANT

35

DC2DC_OUT

30

GN

D

27

GN

D

1

GN

D

9

GN

D

37

GN

D

38

GN

D

39

GN

D

40

GND

16

VBAT_IN

28

GND

31

GN

D

7

VI

O_SOC

8

GN

D

19

GND

34

GN

D

41

GN

D

42

GN

D

43

GN

D

51

GN

D

50

GN

D

49

GN

D

48

GN

D

44

GN

D

45

GN

D

46

GN

D

47

XT

ALM

21

XT

ALP

20

GND

18

GND

29

GND

10

GN

D

22

CLK_REQ_OUT

32

R23
NL_0R

RES1005

VBAT_SYS: 2.7V~4.8V => 3.6V TYP

VBAT_SY S

VBAT_SW_EN

VIO_SOC: 1.62V~1.92V => 1.8V TYP

WL_RX

WL_DBG
WL_TX

C3

NL_10pF

CAP1005

J1
U.FL-R-SMT(10)

U.FL

1

2

3

L2
2.2nH

IND1005

C1

2.2pF

CAP1005

L1
NL

IND1005

C2
10pF

CAP1005

WL_EN1

ANT1

AT8010-E2R9HAA

8.0x1.0x1.0mm

1

2

VIO_CLK

The Antenna matching circuit.

VBAT_IN

VBAT_IN

U2
SN74AVC2T45

XBGA-N8_1X2_0.5-A

VCCA

1

A1

2

A2

3

GND

4

VCCB

8

B1

7

B2

6

DIR

5

VIO_SOC

VIO LDO

NS_UART

U4
SN74AVC2T45

XBGA-N8_1X2_0.5-A

VCCA

1

A1

2

A2

3

GND

4

VCCB

8

B1

7

B2

6

DIR

5

R17

0R

RES1005

WL_SPI_IRQ_1V8
WL_SPI_DOUT_1V8

U5
SN74AVC2T45

XBGA-N8_1X2_0.5-A

VCCA

1

A1

2

A2

3

GND

4

VCCB

8

B1

7

B2

6

DIR

5

WL_SPI_CS_1V8

U6
TPS22913B

XBGA-N4_0.9x0.9_0.5

VIN

A2

VOUT

A1

ON

B2

GND

B1

VBAT_IN

U3
TPS79718

MO-203_2.1x2

GND

2

NC

3

IN

4

OUT

5

PG

1

R9

0R

RES1005

VIO_SYS: Voltage of Host Level

WL_SPI_IRQ_HOST
WL_SPI_DOUT_HOST

-->

C6
1uF

CAP1608

R18
100K

RES1005

-->

VIO_SOC

C4
1uF

CAP1608

-->

DIR High : A data to B bus
DIR Low : B data to A bus

VBAT_SY S

R15
100K

RES1005

VBAT_SY S

C5

0.1uF

CAP1005

WL_SPI_CLK_HOST

WL_SPI_DIN_HOST

WL_SPI_CS_HOST

VBAT_SYS FET SWITCH

WL_SPI_CLK_1V8

WL_SPI_DIN_1V8

WL_EN1

DC2DC_OUT

R3
0R

RES1005

J14

Male 1x3

1

2

3

RTTT Debug

VIO_SOC

Networking Subsystem Debug

NS_UART

DC2DC_OUT

WL Debug Logger

R4
NL_0R

RES1005

VBAT_IN

VIO_SOC

R1
0R

RES1005

32KHz_1V8_HOST

R7

NL_0R

RES1005

SLOW CLK 32.768KHz

OSC1

SG-3030LC/32.768kHz

CY -N12_3.6X2.8_0.5

VI

O

1

VC

C

12

OU

T

7

GN

D

6

NC

2

NC

3

NC

4

NC

5

NC

8

NC

9

NC

10

NC

11

R2

0R

RES1005

J10

Male 1x2

1

2

Connect to Host SPI Interface.
(Host I/O level: VIO_SYS)

Internal Power FET Switch Enable.
Connect to Host GPIO.

VIO_SOC

The 32.768kHz clock select.
Connect to OSC or Host source. 

J16
NL_Male 1x3

1

2

3

R14
NL_0R

RES1005

VIO_SOC

C22
10uF

CAP2012

J11
Male 1x2

1

2

Debug mode => 1-2 short to GND
Functional mode => 2-3 short

WL_EN2

VIO_SOC

EM Connector

J12

Male 1x2

1

2

WL_SPI_CS_1V8

R8

0R

RES1005

R11

0R

RES1005

WL_SPI_IRQ_1V8

R10

0R

RES1005

WL_SPI_CLK_1V8

R13

0R

RES1005

WL_SPI_DIN_1V8

R12

0R

RES1005

WL_SPI_DOUT_1V8

VBAT_SY S

R21

NL_0R

RES1005

32KHz_1V8_HOST

32KHz_1V8_HOST

R20

NL_0R

RES1005

WL_SPI_DIN_HOST

WL_SPI_CLK_HOST

VBAT_SW_EN

WL_SPI_CS_HOST

WL_SPI_DOUT_HOST

WL_SPI_IRQ_HOST

J6
SFM-110-02-L-D-A

pitch 1.27-2x10

1
3
5
7
9

11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

R5
0R

RES1005

VBAT_SY S

J7

SFM-110-02-L-D-A

pitch 1.27-2x10

1
3
5
7
9

11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

R22
0R

RES1005

J13

Male 1x6

1

2

3

4

5

6

VBAT_SY S

VBAT_SY S

VIO_CLK:  3.3V

VBAT_IN

Reserved VIO CLK LDO

VIO_CLK

W

L_R

X

U7
NL_TPS79733

MO-203_2.1x2

GND

2

NC

3

IN

4

OUT

5

PG

1

 

 

Figure 4. Schematics of WG1300BE00 EM Board 

 

 

 
 
 
 
 
 
 
 
 
 
 

Summary of Contents for WG1300-B0

Page 1: ...Copyright JORJIN TECHNOLOGIES INC 2013 http WWW JORJIN COM TW CONFIDENTIAL a module solution provider WG1300 B0 Evaluation Module User Guide Revision 0 2 ...

Page 2: ...TRODUCTION 7 2 WG1300 B0 EM BOARD 7 2 1 TOP SIDE 7 2 2 BOTTOM SIDE 10 2 3 HARDWARE SETUP 12 2 4 SCHEMATICS 13 2 5 BILL OF MATERIAL BOM 14 3 ANTENNA CHARACTERISTICS 15 3 1 RETURN LOSS VSWR 15 3 2 PLANE DEFINITION 15 3 3 3D RADIO PATTERN 16 3 4 2D RADIO PATTERN 17 4 LAYOUT GUIDELINES 18 4 1 BOARD LAYOUT 18 5 APPLICATION DEVELOPMENT 22 6 HISTORY CHANGE 23 ...

Page 3: ...s However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one of the following measures Reorient or relocate the receiving antenna Increase the separation betwe...

Page 4: ... the event that these conditions can not be met for example certain laptop configurations or co location with another transmitter then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product In these circumstances the OEM integrator will be responsible for re evaluating the end product including the transmitter and obtaining a separate FCC authorizat...

Page 5: ...alled and operated with minimum distance 20cm between the radiator your body Déclaration d exposition aux radiations Cet équipement est conforme aux limites d exposition aux rayonnements IC établies pour un environnement non contrôlé Cet équipement doit être installé et utilisé avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps This device is intended only for OEM i...

Page 6: ...le produit final y compris l émetteur et l obtention d une autorisation distincte au Canada End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users The final end product must be labeled in a visible area with the following Contains IC 10462A WG1300B0 Plaque signalétique du p...

Page 7: ...e Le manuel de l utilisateur final doit inclure toutes les informations réglementaires requises et avertissements comme indiqué dans ce manuel Under Industry Canada regulations this radio transmitter may only operate using an antenna of a type and maximum or lesser gain approved for the transmitter by Industry Canada To reduce potential radio interference to other users the antenna type and its ga...

Page 8: ...hardware setup for test to evaluate the performances of CC3000 WG1300 B0 SiP Module 2 WG1300 B0 EM BOARD In the following sub sections it ll divide into TOP and BOTTOM Side to explain details on the key parts and its features 2 1 TOP Side Figure 1 is TOP Side picture of WG1300BE00 EM Board Figure 1 TOP Side of WG1300BE00 EM Board The picture above marks some key parts and jumpers and Table 1 J10 J...

Page 9: ...pin 2 are shorted 5 J10 It is a jumper for testing power consumption It is for the power for all circuit in this board In operation mode pins of the jumper is shorted For power testing the jumper is removed and ammeter crosses the pins to do the testing 6 J12 It is a jumper for testing VBAT_IN power consumption of WG1300 B0 In operation mode pins of the jumper is shorted For power testing the jump...

Page 10: ...working subsystem UART Debug line 5 DC2DC_OUT P Internal DC2DC output power 6 GND Ground Table 2 TOP Side J13 of WG1300BE00 EM Board Table 3 below shows the signal descriptions of J16 Pin Number Pin Name Pin Type Descriptions 1 GND Ground 2 SDA_EEPROM I O I2C Data signal from EEPROM inside CC3000 WG1300 B0 SiP Module This pin is connected to SDA_CC3000 via a 0 Ohm resister and is not used by end u...

Page 11: ...onnecting to Host platform and mounted on the bottom side as the picture above Table 4 and Table 5 show the descriptions on the signals brought out from these two EM mating connectors J6 Pin Number Pin Name Module Pin Type Description 1 GND Ground 5 EXT_32KHz I External Slow Clock input from Host device It can be used for the SiP Module inside which hasn t slow clock source 10 VBAT_SW_EN I Active ...

Page 12: ... 18 WL_SPI_DIN I Host Interface SPI Data Input 19 GND Ground 20 WL_SPI_DOUT O Host interface SPI Data Ouput Table 4 BOTTOM Side J6 of WG1300BE00 EM Board J7 Pin Number Pin Name Module Pin Type Description 2 GND Ground 7 VBAT_IN PI Battery voltage input to Module 9 VBAT_IN PI Battery voltage input to Module 15 EXT_32KHz I External Slow Clock input from Host device Table 5 BOTTOM Side J7 of WG1300BE...

Page 13: ...Hardware Setup Before conducting performance test EM Board should be connected to Host platform with mating connectors J6 and J7 For the case of using EM mating connector for hardware connection the mating EM connector should be lined up and spaced 1 2 apart as Figure 3 below Figure 3 Host PCB Mating Connector Arrangement ...

Page 14: ...1 R9 0R RES1005 VIO_SYS Voltage of Host Level WL_SPI_IRQ_HOST WL_SPI_DOUT_HOST C6 1uF CAP1608 R18 100K RES1005 VIO_SOC C4 1uF CAP1608 DIR High A data to B bus DIR Low B data to A bus VBAT_SYS R15 100K RES1005 VBAT_SYS C5 0 1uF CAP1005 WL_SPI_CLK_HOST WL_SPI_DIN_HOST WL_SPI_CS_HOST VBAT_SYS FET SWITCH WL_SPI_CLK_1V8 WL_SPI_DIN_1V8 WL_EN1 DC2DC_OUT R3 0R RES1005 J14 Male 1x3 1 2 3 RTTT Debug VIO_SOC...

Page 15: ...tch TPS22913BYZV 5 OSC1 OSC 3225 32 768KHz 1 5 5 5V 5ppm 6 ANT1 ANT 2 4GHZ Peak Gain 2 5DB 7 J10 J11 J12 CON Male 1x2 Pitch 2 0 mm 8 J14 CON Male 1x3 Pitch 2 0 mm 9 J6 J7 Female Header Fool Proof H 4 3 2x10 Pitch 1 27mm SMT 10 J1 Mini RF Header Receptacle 11 R1 R2 R3 R5 R8 R9 R10 R11 R12 R13 R17 R22 RES 0402 0R 5 12 R15 R18 RES 0402 100K 5 13 L2 IND 0402 2 2nH 0 3nH 0 16ohm 300mA 14 C1 CAP 0402 2 ...

Page 16: ...rd UG R02 Copyright JORJIN TECHNOLOGIES INC 2014 http WWW JORJIN COM TW CONFIDENTIAL Page 15 3 ANTENNA CHARACTERISTICS 3 1 Return Loss VSWR Figure 5 Antenna return loss VSWR 3 2 Plane Definition Figure 6 Plane Definition Y Z X ...

Page 17: ...o WG1300BE00 EM Board UG R02 Copyright JORJIN TECHNOLOGIES INC 2014 http WWW JORJIN COM TW CONFIDENTIAL Page 16 3 3 3D Radio Pattern Figure 7 3D Radio Pattern XY Plane Theta 90 XZ Plane Phi 0 YZ Plane Phi 90 ...

Page 18: ...yright JORJIN TECHNOLOGIES INC 2014 http WWW JORJIN COM TW CONFIDENTIAL Page 17 3 4 2D Radio Pattern Figure 8 2D Radio Pattern Table 7 Gain Table XY Plane XZ Plane YZ Plane Efficiency Peak Avg Peak Avg Peak Avg 0 3 2 6 1 3 4 2 0 9 0 9 66 7 ...

Page 19: ...e 8 and Figure 10 describe instances of good layout practices Reference Guideline Descriptions 1 The proximity of ground vias must be close to the pad 2 Signal traces must not be run underneath the module on the layer where the module is mounted 3 Increase the ground pour in the first layer 4 Have a solid ground plane and ground vias under the module for stable system and thermal dissipation Table...

Page 20: ... for the PCB A 50 Ω impedance match on the trace to the antenna should be used Also 50 Ω traces are recommended for the PCB layout Figure 11 also lists the distances Figure 12 shows layer 1 with the trace to the antenna over the layer 2 Table 9 and Figure 13 describe instances of good layout practices for the antenna and RF trace routing Figure 11 Trace Design for the PCB layout 1 2 3 4 ...

Page 21: ...he ground plane beside the RF trace on both sides 4 RF traces must have constant impedance microstrip transmission line 5 For best results the RF trace ground layer must be the ground layer immediately below the RF trace The ground layer must be solid 6 There must be no traces or ground under the antenna section 7 The PCB designer must understand the microstrip model used and the scale line width ...

Page 22: ...ting Layout Guidelines The following show the supply routing guidelines For power supply routing the power trace for VBAT must be at least 40 mil wide The 1 8 V trace must be at least 18 mil wide Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance If possible shield VBAT traces with ground above below and beside the traces 1 2 3 4 5 5 6 8 ...

Page 23: ...tform MSP EXP430FR5730 for evaluating CC3000 based SiP Module Figure 4 shows the platform and WG1300BE00 EM Board Figure 4 MSP EXP430FR5730 and WG1300BE00 EM Board The MSP EXP430FR5739 test platform can be ordered as the link below http www ti com tool msp exp430fr5739 Specific application examples can refer to the link below http processors wiki ti com index php CC3000 Wi Fi for MCU ...

Page 24: ...UG R02 Copyright JORJIN TECHNOLOGIES INC 2014 http WWW JORJIN COM TW CONFIDENTIAL Page 23 6 HISTORY CHANGE Revision Date Description R 0 1 2013 7 22 Release 0 1 R 0 2 2014 May 22 Add 3 Antenna Characteristics 4 Layout Guidelines ...

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