JHCTech FEBC-3158, User Manual, Page: 41 / 64

User’s Manual
34
Active LFP
[Int-LVDS]
[No LVDS]
[SDVO LVDS]
[eDP Port-A]
[eDP Port-D]
Panel Color Depth
[24 Bit]
[18 Bit]
>DMI Configuration
>NB PCIe Configuration
PEG0 [Not Present]
PEG0
–
Gen X [Auto]
[Gen1]
[Gen2]
[Gen3]
PEG0
–
ASPM [Auto]
[Disabled]
[ASPM Los]
[ASPM L1]
[ASPM LosL1]
Enable PEG [Auto]
Detect Non-Compliance Device
[Disabled]
De-emphasis Control
[-3.5 dB]
[-6 dB]
PEG Sampler Calibrate [Auto]
Swing Control [Full]
Gen3 Equalization [Enabled]
Gen3 Eq Phase 2 [Auto]
PEG Gen3 Root Port Preset Value for each Lane
PEG Gen3 Endpoint Preset Value for each Lane
PEG Gen3 Endpoint Hint Value for each Lane
Gen3 Eq Preset Search [Disabled]
PEG Link Disabled [Disabled]
Fast PEG Init [Enabled]
RxCEM Loop back [Disabled]
PCIe Gen3 RxCTLEp Setting
>Memory Configuration
Memory RC Version 1.2.2.0
Memory Frequency 1333 Mhz
Total Memory 2048 MB (DDR3)
DIMM#0 2048 MB (DDR3)
DIMM#2 Not Present
CAS Latency (tCL) 9
Minimum delay time
CAS to RAS (tRPmin) 9