27
The default setting is “
↓
16
↑
16
” for this selection, and it provides with the adjustable
bandwidth selection for you to choose the combination of stream with x16 and x16 bandwidth
of updoad and down between the processor and system chip.
DRAM Timing Settings
Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
3-6-1 DRAM Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Item Help
Auto Configuration Auto
DRAM CAS Latency CL=2.5
RAS Active Time 8T
RAS Precharge Time 2T
RAS To CAS Delay 4T
Bottom of 32-Bit[31:24]IO EO
DRAM Command Rate 2T
S/W memory hole Remapping Disabled
H/W Memory Hole Remapping Disabled
MTRR Mapping Mode Continuous
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 4T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
