26
3-6-1 DRAM Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Item Help
Auto Configuration Auto
x DRAM CAS Latency CL=2.5
x RAS Active Time 8T
x RAS to CAS Delay 4T
x RAS Precharge Time 4T
x DRAM Bank Interleaving Enabled
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 4T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
3-6-2 AGP Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
AGP Timing Settings
Item Help
AGP Aperture Size 128M
AGP Transfer Mode 8X
AGP Driving Control Auto
X AGP Driving Value AA
AGP Fast Write Disabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
CPU to AGP Post Write Enabled
AGP Delay Transaction Disabled
AGP 3.0 Calibration Cycle Enabled
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
