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3-6-1 Advanced DRAM Control
The “Advanced DRAM Control” includes settings for the chipset dependents features.
These features are related to system performance. Make sure you fully understand the
items contained in this menu before you try to change anything. You may change the
parameter settings to improve system performance. However, it may cause your
system to be unstable if the setting is not correct for your system configuration.
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Advanced DRAM Control
Item Help
Auto Configuration [Optimized]
Precharge Command 3T
Active to CMD Command 6T
Write Recovery Time 2T
SDRAM Cycle Length By SPD
Bank Interleave By SPD
DRAM Drive Strength Auto
Delay DRAM Read Latch 1.0 ns
Memory Data Drive Normal
Memory CMD Drive Strong
DDSKEW/REFCLK Delay No Delay
In-Order Queue 1-Level
P2C/C2P Concurrency Disabled
Fast R-W Turn Around Disabled
I/O Recovery Time Disabled
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Disabled
PCI Master 0 WS Write Disabled
PCI Delay Transaction Disabled
PCI#2 Access #1 Retry [Disabled]
Menu Level >>
↑↓→←
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Precharge Command
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2 and 3.
Active Command
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2 and 3.
Active to CMD Command
Select the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.
SDRAM Cycle Length
