Jennic JN5142, Datasheet

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© NXP Laboratories UK 2012 JN-DS-JN5142 1v0 35
10 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5142 and
peripheral devices. The JN5142 operates as a master on the SPI bus and all other devices connected to the SPI are
expected to be slave devices under the control of the JN5142 CPU. The SPI includes the following features:

Full-duplex, three-wire synchronous data transfer

Programmable bit rates (up to 16Mbit/s)

Programmable transaction size up to 32-bits

Standard SPI modes 0,1,2 and 3

Manual or Automatic slave select generation (up to 3 slaves)

Maskable transaction complete interrupt

LSB First or MSB First Data Transfer

Supports delayed read edges
Clock
Divider
SPI Bus
Cycle
Controller
Data Buffer
DIV Cl
oc
k
E
dg
e
S
el
ec
t
Data CHAR_
LE
N
LS
B
SPIMISO
SPIMOSI
SPICLK
Select
Latch
SPISEL [2..0]
16 MHz
Figure 23: SPI Block Diagram
The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices
in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously.
There are three dedicated pins SPICLK, SPIMOSI, SPIMISO that are shared across all devices on the bus. Master-
Out-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN5142.
The JN5142 provides three slave selects, SPISEL0 to SPISEL2 to allow three SPI peripherals on the bus. SPISEL0
is a dedicated pin; this is generally connected to a serial Flash/EEPROM memory holding application code that is
downloaded to internal RAM via software from reset. SPISEL1 is accessed, depending upon the configuration, on
DIO0 or DIO14. SPISEL2 is accessed on DIO1 or DIO15. This is enabled under software control. The following table
details which DIO are used for the SPISEL signals depending upon the configuration.
Signal
DIO Assignment
Standard pins Alternative pins
SPISEL1 16 38
SPISEL2
17 40
Table 3: SPISEL IO
The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted
between transfers when required, to enable longer transfers to be performed.
When the device reset is active, the three outputs SPISEL, SPICLK and SPI_MOSI are tri-stated and SPI_MISO is
set to be an input. The pull-up resistors associated with all four pins will be active at this time.