IWILL VX133, Manual

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Chapter 4 BIOS Setup
4.6.4 Memory Hole
In order to improve performance, certain space in memory is
reserved for ISA cards. This memory must be mapped into
the memory space below 16MB.
d e l b a s i D , M 6 1 - M 5 1 ) e u l a V t l u a f e D (
4.6.5PCI Dynamic Bursting
When enabled, every write transaction goes to the write
buffer, and burstable transactions will then burst on the PCI
bus, and non-burstable transactions won’t burst on the PCI
bus.
When disabled, if the write transaction is a burst transaction,
the information goes into the write buffer and burst transfers
are later performed on the PCI bus. If the transaction is not
a burst transaction, PCI write occurs immediately (after a
write buffer flush).
e l b a n E ) e u l a V t l u a f e D ( d e l b a s i D ,
4.6.6 Delayed Transaction
The chipset has embedded 32-bit posted writer buffer to
support delayed transaction cycles. When enable, the
system is compliant with PCI specificationversion 2.2.
e l b a n E ) e u l a V t l u a f e D ( d e l b a s i D ,
4.6.7System BIOS Cacheable
When enable accesses to the system BIOS will be cached
e l b a n E ) e u l a V t l u a f e D ( d e l b a s i D ,
4.6.8 Video RAM Cacheable
When enabled, access to the video memory located at
A0000H to BFFFFH will be cached.