57
VD133 Pro Series
Chapter 5 BIOS Setup
5.5.6 P2C/C2P Concurrency
When disabled, P2C/C2P will be occupied during the entire P2C/C2P operation period.
Options
Enabled
Disabled (*)
5.5.7 CPU to PCI Write Buffer
When this field is enabled, CPU data is written to a write buffer prior to being sent to
the PCI bus, in order to compensate for the speed differences between the CPU and
the PCI bus. When disabled, the CPU data is sent directly to the PCI bus, however,
because the CPU operates at a faster speed than the PCI bus, the CPU must wait as the
PCI bus receives data before beginning each write cycle.
Options
Enabled (*)
Disabled
5.5.8 PCI Dynamic Bursting
When enabled, every write transaction goes to the write buffer, and burstable
transactions will then burst on the PCI bus, and non-burstable transactions won’t
burst on the PCI bus.
When disabled, if the write transaction is a burst transaction, the information goes
into the write buffer and burst transfers are later performed on the PCI bus. If the
transaction is not a burst transaction, PCI write occurs immediately (after a write
buffer flush).
Options
Enabled (*)
Disabled
5.5.9 Delay Transaction
The chipset has embedded 32-bit posted writer buffer to support delayed transaction
cycles. When enable, the system is compliant with PCI specificationversion 2.1
Options
Enabled (*)
Disabled
5.5.10 System BIOS cacheable
When enable accesses to the system BIOS will be cached
Option
Enable(*)
Disable
