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Memory Parity / ECC Check
This item allows you to select between three methods of memory error checking, Auto,
Enabled and Disabled
Single Bit Error Report
L2 Cache Cacheable Size
When a single bit error is detected, the offending DRAM row ID is latched . The
latched Valued is held until software explicit clears the error status flag. You can select
Enabled or Disabled.
This item determines the size of the L2 cacheability: 64MB / 512MB .
Chipset NA# Asserted
This item allows you to select between two method of chipset NA# asserted during CPU
write cycles /CPU line fills, Enabled and Disabled.
Pipeline Cache Timing
This item allows you to select two timing of pipeline cache, Faster and Fastest.
Tag Ram Size
8 bit for 64 MByte cacheable memory; 9 bit for 128 MByte cacheable;
10 bit for 256 MByte; 11 bit for 512 Mbyte.
You need to install an extra 32K8 Tag Ram on U11 if over 64 Mbyte cacheable
is needed.
U11
Summary of Contents for P55XPLUS
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