IWILL P55XPLUS, Manual

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X s u l P
T M
Turbo Read Leadoff
The turbo read leadoff may be required in certain system designs to support layouts or
faster memories.
Disabled is the default.
DRAM Speculative Leadoff
The ALI Aladdin 4+ chipset is capable of allowing a DRAM read request to be
generated slightly before the address has been fully decoded. This can reduce all read
latencies.
More simply, the CPU will issue a read request and included with this request is the
place (address) in memory where the desired data is to be found. This request is
received by the DRAM controller. When the peculative Leadoff ’ is enabled, the
controller will issue the read command slightly before it has finished determining the
address.
Disabled is the default.
Turn-Around Insertion
When this is enabled, the chipset will insert one extra clock to the turn-around of back-
to-back DRAM cycles.
Disabled is the default.
ISA Clock
This item allows you to select the PCI clock type.
PCI CLK/3 PCI clock type
PCI CLK/4 PCI clock type
Cache Features
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are
cached, provided that the cache controller is enabled.
Enabled BIOS access cached
Disabled BIOS access not cached
Disabled is the default.
Video BIOS Cacheable
As with caching the System BIOS above, enabling the Video BIOS cache will cause
access to video BIOS addressed at C0000H to C7FFFH to be cached, if the cache
controller is also enabled