iWave iW-RainboW-G33M, Hardware User'S Manual

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REL0.1
Page 48 of 58
i.MX8 SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.11 i.MX8M Pin Multiplexing on Expansion Connector
The below table provides the details of i.MX8M Processor pin connections to the Expansion connector with selected pin function highlighted and available
alternate functions. This table has been prepared by referring NXP’s i.MX8M Hardware User’s Manual.
Table 9: i.MX8M
Pin Multiplexing on
Expansion Connector interfaces
Interface/
Function
Expan.
Conn.
Pin
Number
i.MX8M
CPU
Pin
Number
Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 GPIO
Default
State
SAI
49 L1 sai1.RX_SYNC sai5.RX_SYNC coresight.TRACE_CLK gpio4.IO[0] gpio4.IO[0]
LVDS1_CH0_CLK_N
55 K1 sai1.RX_BCLK sai5.RX_BCLK coresight.TRACE_CTL gpio4.IO[1] gpio4.IO[1]
LVDS1_CH0_CLK_P
35 K2 sai1.RX_DATA[0] sai5.RX_DATA[0] coresight.TRACE[0] gpio4.IO[2] gpio4.IO[2]
LVDS1_CH0_TX0_N
37 L2 sai1.RX_DATA[1] sai5.RX_DATA[1] coresight.TRACE[1] gpio4.IO[3] gpio4.IO[3]
LVDS1_CH0_TX0_P
39 H2 sai1.RX_DATA[2] sai5.RX_DATA[2] coresight.TRACE[2] gpio4.IO[4] gpio4.IO[4]
LVDS1_CH0_TX1_N
47 J2 sai1.RX_DATA[3] sai5.RX_DATA[3] coresight.TRACE[3] gpio4.IO[5] gpio4.IO[5]
LVDS1_CH0_TX1_P
43 J1 sai1.RX_DATA[4] sai6.TX_BCLK sai6.RX_BCLK coresight.TRACE[4] gpio4.IO[6] gpio4.IO[6]
LVDS1_CH0_TX2_N
41 F1 sai1.RX_DATA[5] sai6.TX_DATA[0] sai6.RX_DATA[0] sai1.RX_SYNC coresight.TRACE[5] gpio4.IO[7] gpio4.IO[7]
LVDS1_CH0_TX2_P
53 G2 sai1.RX_DATA[6] sai6.TX_SYNC sai6.RX_SYNC coresight.TRACE[6] gpio4.IO[8] gpio4.IO[8]
LVDS1_CH0_TX3_N
45 G1 sai1.RX_DATA[7] sai6.MCLK sai1.TX_SYNC sai1.TX_DATA[4] coresight.TRACE[7] gpio4.IO[9] gpio4.IO[9]
LVDS1_CH0_TX3_P
19 H1 sai1.TX_SYNC sai5.TX_SYNC coresight.EVENTO gpio4.IO[10] gpio4.IO[10] LVDS1_CH1_CLK_N
21 E1 sai1.TX_BCLK sai5.TX_BCLK coresight.EVENTI gpio4.IO[11] gpio4.IO[11] LVDS1_CH1_CLK_P
1 F2 sai1.TX_DATA[0] sai5.TX_DATA[0] coresight.TRACE[8] gpio4.IO[12] gpio4.IO[12] LVDS1_CH1_TX0_N
15 E2 sai1.TX_DATA[1] sai5.TX_DATA[1] coresight.TRACE[9] gpio4.IO[13] gpio4.IO[13] LVDS1_CH1_TX0_P
5 B2 sai1.TX_DATA[2] sai5.TX_DATA[2] coresight.TRACE[10] gpio4.IO[14] gpio4.IO[14] LVDS1_CH1_TX1_N
7 D1 sai1.TX_DATA[3] sai5.TX_DATA[3] coresight.TRACE[11] gpio4.IO[15] gpio4.IO[15] LVDS1_CH1_TX1_P
9 D2 sai1.TX_DATA[4] sai6.RX_BCLK sai6.TX_BCLK coresight.TRACE[12] gpio4.IO[16] gpio4.IO[16] LVDS1_CH1_TX2_N
11 C2 sai1.TX_DATA[5] sai6.RX_DATA[0] sai6.TX_DATA[0] coresight.TRACE[13] gpio4.IO[17] gpio4.IO[17] LVDS1_CH1_TX2_P
3 B3 sai1.TX_DATA[6] sai6.RX_SYNC sai6.TX_SYNC coresight.TRACE[14] gpio4.IO[18] gpio4.IO[18] LVDS1_CH1_TX3_N
13 C1 sai1.TX_DATA[7] sai6.MCLK coresight.TRACE[15] gpio4.IO[19] gpio4.IO[19] LVDS1_CH1_TX3_P
MIPI CSI0
80
BE25 MIPI_CSI1_D2_P MIPI_CSI1_D2_P
82
BF24 MIPI_CSI1_D2_N MIPI_CSI1_D2_N
86
BE17 MIPI_CSI1_D3_P MIPI_CSI1_D3_P
88
BF16 MIPI_CSI1_D3_N MIPI_CSI1_D3_N