iWave iW-RainboW-G33M Hardware User'S Manual Download

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Page 21 of 58

i.MX8M SMARC SOM Hardware User Guide

iWave Systems Technologies Pvt. Ltd.

Signal

SMARC Pin

(Top)

SMARC Pin

(Bottom)

Signal

I2C1_SCL*

P121

S122

I2C1_SDA*

P122

S123

BOOT_SEL0#

P123

S124

GND

BOOT_SEL1#

P124

S125

MIPI_DSI_DATA0_P

BOOT_SEL2#

P125

S126

MIPI_DSI_DATA0_N

GPIO_RESET_OUT(GPIO3_25)

P126

S127

GPIO_LCD0_1_EN(GPIO3_17)

RESET_IN#

P127

S128

MIPI_DSI_DATA1_P

POWER_BUTTON

P128

S129

MIPI_DSI_DATA1_N

UART2_TXD

P129

S130

GND

UART2_RXD

P130

S131

MIPI_DSI_DATA2_P

UART2_RTS_B

P131

S132

MIPI_DSI_DATA2_N

UART2_CTS_B

P132

S133

GPIO_LCD0_VDD_EN(GPIO3_18)

GND

P133

S134

MIPI_DSI_CLK_P

UART3_RXD

P134

S135

MIPI_DSI_CLK_N

UART3_TXD

P135

S136

GND

UART4_TX

P136

S137

MIPI_DSI_DATA3_P

UART4_RX

P137

S138

MIPI_DSI_DATA3_N

UART4_RTS_B

P138

S139

I2C4_SCL

UART4_CTS_B

P139

S140

I2C4_SDA

UART1_TXD

P140

S141

GPIO_LCD0_BL_PWM(GPIO1_14)

UART1_RXD

P141

S142

GND

P142

S143

GND

P143

S144

GPIO_WDT_OUT(GPIO1_02)*

P144

S145

GPIO_WDT_OUT(GPIO1_02)

P145

S146

PCIE_WAKE_3V3(GPIO5_5)

P146

S147

VDD_RTC

VDD_IN

P147

S148

VDD_IN

P148

S149

VDD_IN

P149

S150

VIN_PWR_BAD#

VDD_IN

P150

S151

VDD_IN

P151

S152

VDD_IN

P152

S153

CARRIER_STBY#

VDD_IN

P153

S154

CARRIER_PWR_ON

VDD_IN

P154

S155

FORCE_RECOV#

VDD_IN

P155

S156

VDD_IN

P156

S157

TEST#

S158

GND

Summary of Contents for iW-RainboW-G33M

Page 1: ...2 Page 1 of 58 i MX8M SMARC SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G33M i MX8M Quad QuadLite Dual SMARC System On Module Hardware User Guide DRAFT VERSION SUBJECT TO CH...

Page 2: ...ns proprietary material for the sole use of the intended recipient s Do not read this document if you are not the intended recipient Any review use distribution or disclosure by others is strictly pro...

Page 3: ...ata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only Certifi...

Page 4: ...ional 15 2 5 4 QSPI Flash Optional 16 2 6 Network Communiation 16 2 6 1 Wi Fi and Bluetooth Interface 16 2 7 SMARC PCB Edge Connector 17 2 7 1 Gigabit Ethernet 22 2 7 2 SD Interface 24 2 7 3 USB Inter...

Page 5: ...ION 50 3 1 Electrical Characteristics 50 3 1 1 Power Input Sequencing 50 3 1 2 Power Consumption 51 3 2 Environmental Characteristics 52 3 2 1 Environmental Specification 52 3 2 2 Heat Sink 52 3 2 3 R...

Page 6: ...Figure 9 i MX8M SMARC Development Platform 57 List of Tables Table 1 Acronyms Abbreviations 7 Table 2 Terminology 9 Table 3 SMARC Edge Connector Pinouts 18 Table 4 Expansion Connector Pinouts 36 Tabl...

Page 7: ...sh power sequencing CPU power supplies GBE and dual channel LVDS display transmitter are concentrated on the Module The Modules are used with application specific Carrier Boards that implement other f...

Page 8: ...ata Rate4 LVDS Low voltage differential signalling MHz Mega Hertz MIPI Mobile Industry Processor Interface PCB Printed Circuit Board RoHS Restriction of Hazardous Substances RTC Real Time Clock RTS Re...

Page 9: ...ow Voltage Differential Signal GBE Gigabit Ethernet Media Dependent Interface differential pair signals USB Universal Serial Bus differential pair signals MIPI Mobile Industry Processor Interface sign...

Page 10: ...same functionality If CPU pin has multiplexing option and selected particular function other than default option then the signal name is mentioned as Selected Function Name CPU Pad name Example UART2...

Page 11: ...NET MicroSD Optional WiFi BT PCIe2 PCIe1 PCIe x 1 USB2 0 HUB USB2 USB2 0 Host x 4 USB1 USB3 0 OTG x 1 USB2 0 OTG x 1 uSDHC2 HDMI TX HDMI x 1 MIPI DSI MIPI DSI x 1 MIPI CSI0 1 MIPI CSI x 2 1 x2 lane 1...

Page 12: ...Cortex M4F Power PF4210 PMIC Memory LPDDR4 2GB Expandable eMMC Flash 8GB Expandable 1 Micro SD slot Optional 1 QSPI Flash Optional Other On SOM Features Wi Fi BT Module2 Gigabit Ethernet PHY Transcei...

Page 13: ...o both eMMC Flash and MicroSD connector So either one feature only can be supported at a time in the SOM and by default eMMC is supported 2 In i MX8M SMARC SOM SD2 interface signals are connected to b...

Page 14: ...of up to 1 5 GHz A general purpose Cortex M4 core processor is for low power processing The DRAM controller supports 32 bit 16 bit LPDDR4 DDR4 and DDR3L memory There are a number of other interfaces f...

Page 15: ...of the SOM LPDDR4 memory size can be customised based on the requirement by contacting iWave support team 2 5 2 eMMC Flash The i MX8M SMARC SOM supports 8GB eMMC as default boot device and storage de...

Page 16: ...etooth 4 0 compliant module optimized for low power mobile applications This module supports single stream 1x1 IEEE 802 11n mode providing up to 72 Mbps PHY rate The ATWILC3000 MR110CA module features...

Page 17: ...PCB edge connector has standard pin out as per SMARC Specification V2 0 The interfaces which are available at 314pin SMARC Edge connector are explained in the following sections Figure 3 SMARC Edge Co...

Page 18: ...TA2_N P14 S14 MIPI_CSI1_DATA1_P GND P15 S15 MIPI_CSI1_DATA1_N MIPI_CSI2_DATA3_P P16 S16 GND MIPI_CSI2_DATA3_N P17 S17 GBE1_MDI0 GND P18 S18 GBE1_MDI0 GBE0_MDI3 P19 S19 GBE1_LINK100 GBE0_MDI3 P20 S20 G...

Page 19: ...NAND_CLE P56 S56 QSPI_B_DATA2 NAND_DATA06 QSPI_B_DATA0 NAND_DATA04 P57 S57 QSPI_B_DATA3 NAND_DATA07 QSPI_B_DATA1 NAND_DATA05 P58 S58 GPIO_QSPI_RST GPIO3_15 GND P59 S59 USB_HUB4OUT_DP USB0_DP P60 S60...

Page 20: ...HDMI_TX_DATA1_N GND P97 S98 NC HDMI_TX_DATA0_P P98 S99 HDMI_TX_DATA2_P HDMI_TX_DATA0_N P99 S100 HDMI_TX_DATA2_N GND P100 S101 GND HDMI_TX_CLK_P P101 S102 HDMI_CLK_P HDMI_TX_CLK_N P102 S103 HDMI_CLK_N...

Page 21: ...B P132 S133 GPIO_LCD0_VDD_EN GPIO3_18 GND P133 S134 MIPI_DSI_CLK_P UART3_RXD P134 S135 MIPI_DSI_CLK_N UART3_TXD P135 S136 GND UART4_TX P136 S137 MIPI_DSI_DATA3_P UART4_RX P137 S138 MIPI_DSI_DATA3_N UA...

Page 22: ...IEEE 802 3 compliant Media Access Controller MAC with a triple speed Ethernet transceiver PCIe bus controller and embedded memory With state of the art DSP technology and mixed mode signal technology...

Page 23: ...NA IO GBE Second Gigabit Ethernet MDI differential pair 0 negative S19 GBE1_LINK100 NA O 3 3V CMOS 100Mbps Ethernet link status LED Note Connect to Cathode of LED S20 GBE1_MDI1 NA IO GBE Second Gigab...

Page 24: ...CMOS 10K PU SD Power enable P39 SD2_ DATA0 SD2_ DATA0 N22 IO 1 8 3 3V CMOS SD data 0 line P40 SD2_ DATA1 SD2_ DATA1 N21 IO 1 8 3 3V CMOS SD data 1 line P41 SD2_ DATA2 SD2_ DATA2 P22 IO 1 8 3 3V CMOS S...

Page 25: ...P71 USB2_EN_OC NA IO 3 3V CMOS 10K PU USB Port2 Power Enable Over Current Indicator Note Connected to USB Hub P74 USB3_EN_OC NA IO 3 3V CMOS 10K PU USB Port3 Power Enable Over Current Indicator Note C...

Page 26: ...ne is directly connected to PCIeA port of SMARC Edge connector whereas PCIe1 is connected to on SOM PCIe to Ethernet controller in the default configuration but option is provided to connect to PCIeB...

Page 27: ...4 virtual channels and all data types The Local interface runs at the User Interface clock rate for all implementations The CSI 2 Rx Controller Core takes care of all packet formatting details and tra...

Page 28: ...Ball Name Pin Number Signal Type Termination Description S1 I2C1_SCL I2C1_SCL E7 O 1 8V CMOS 4 7K PU MIPI CSI1 I2C Clock S2 I2C1_SDA I2C1_SDA E8 IO 1 8V CMOS 4 7K PU MIPI CSI1 I2C Data P3 MIPI_CSI2_CL...

Page 29: ...P98 HDMI_TX_DATA0_P HDMI_TX_DATA0_P T1 O HDMI HDMI Transceiver 0 Positive P99 HDMI_TX_DATA0_N HDMI_TX_DATA0_N T2 O HDMI HDMI Transceiver 0 Negative P101 HDMI_CLK_P HDMI_CLK_P M1 O HDMI HDMI Transceive...

Page 30: ...I_DSI_DATA3_P B15 O MIPI MIPI DSI0 differential data lane 3 positive S138 MIPI_DSI_DATA3_N MIPI_DSI_DATA3_N A15 O MIPI MIPI DSI0 differential data lane 3 negative S139 I2C4_SCL I2C4_SCL F8 O 1 8V CMOS...

Page 31: ...erface The i MX8M CPU supports low power Serial Peripheral Interface SPI module that supports an efficient interface to an SPI bus as a master and or a slave with maximum clock speed of 20MHz with SPI...

Page 32: ...cted to SER2 channel of SMARC Edge connector by default UART1 is connected to on SOM Bluetooth module SER0 SER1 SER2 can be used for any data commination UART4 of the CPU is connected to SER3 channel...

Page 33: ...pe Termination Description P108 SMARC_GPIO_0 GPIO3_16 GPIO3_16 K20 IO 1 8V CMOS SMARC General Purpose Input output 0 P109 SMARC_GPIO_1 GPIO1_12 GPIO1_12 L7 IO 1 8V CMOS SMARC General Purpose Input out...

Page 34: ...OFF W21 I 1 8V CMOS 100K PU Power ON OFF Input to SOM S150 VIN_PWR_BAD NA I 5V CMOS 10K PU Power bad indication from Carrier board Module and Carrier power supplies shall not be enabled while this sig...

Page 35: ...No SMARC Edge Signal Name CPU Ball Name Pin Number Signal Type Termination Description P2 P9 P12 P15 P18 P32 P38 P47P50 P53 P59 P68 P79 P82P85 P88 P91 P94 P97 P100 P103 P120 P133 P142 S3 S10 S13 S16...

Page 36: ...ector FX8C 100P SV 91 from Hirose Table 4 Expansion Connector Pinouts Signal Expansion Connector Pin Expansion Connector Pin Signal SAI1_TXD0 1 2 NC SAI1_TXD6 3 4 NC SAI1_TXD2 5 6 GND SAI1_TXD3 7 8 NC...

Page 37: ...5_2 GND 65 66 GND NC 67 68 GPIO_BCONFIG_2 GPIO4_29 NC 69 70 NC NC 71 72 GND NC 73 74 NC GND 75 76 GPIO_BCONFIG_1 GPIO4_28 GPIO_BCONFIG_4 GPIO4_22 77 78 GND NC 79 80 MIPI_CSI1_DATA2_P NC 81 82 MIPI_CSI...

Page 38: ...oot media selection 7 SAI1_TXD3 SAI1_TXD3 D1 O 1 8V CMOS 10K PD SAI1 Transmit Data 3 9 SAI1_TXD4 SAI1_TXD4 D2 O 1 8V CMOS 10K PD 1K PU SAI1 Transmit Data 4 Note Termination will differ based on boot m...

Page 39: ...port one two lane and one four lane MIPI CSI hence data2 and data3 lane of CSI0 channel are connected to board expansion connector For more details on MIPI CSI expansion signals refer below table Exp...

Page 40: ...art 0530480210 from Molex Mating Connector 51021 0200 from Molex Compatible FAN Example AFB0505MB from Delta Electronics Table 5 FAN Header Pin Assignment Pin No Signal Name Signal Type Termination De...

Page 41: ...GRPB102MWCN RC from Sullins Connector Solutions Mating Connector LPPB102CFFN RC from Sullins Connector Solutions Table 6 JTAG Header Pin Assignment Optional Pin No Signal Name Signal Type Termination...

Page 42: ...8 to 3 3 voltage level translator FTDI s UART to USB smart cable TTL 232R RPI can be directly connected between this header and Host PC for debugging This is the optional feature and will not be popul...

Page 43: ...IOMUX for SMARC Edge Connector interfaces Interface Function SMARC Edge Pin Number i MX8M CPU Pin Number Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 GPIO Default State MIPI CSI0...

Page 44: ...I_D3_N S137 B15 MIPI_DSI_D3_P MIPI_DSI_D3_P S139 BD38 i2c4 SCL pwm2 OUT pcie1 CLKREQ_B gpio5 IO 20 gpio5 IO 20 i2c4 SCL S140 BD36 i2c4 SDA pwm1 OUT pcie2 CLKREQ_B gpio5 IO 21 gpio5 IO 21 i2c4 SDA S141...

Page 45: ...56 L19 rawnand DATA06 qspi B_DATA 2 gpio3 IO 12 gpio3 IO 12 qspi B_DATA 2 S57 M19 rawnand DATA07 qspi B_DATA 3 gpio3 IO 13 gpio3 IO 13 qspi B_DATA 3 P58 L20 rawnand DATA04 qspi B_DATA 0 gpio3 IO 10 gp...

Page 46: ...CTS_B gpio5 IO 12 gpio5 IO 12 uart4 CTS_B UART4 P141 C7 uart1 RX ecspi3 SCLK gpio5 IO 22 gpio5 IO 22 uart1 RX P140 A7 uart1 TX ecspi3 MOSI gpio5 IO 23 gpio5 IO 23 uart1 TX Audio SAI0 S52 F3 sai3 RX_D...

Page 47: ...sdhc1 CD_B gpio1 IO 6 gpio1 IO 6 P116 N7 gpio1 IO 8 enet1 1588_EVENT 0_IN usdhc2 RESET _B gpio1 IO 8 gpio1 IO 8 P117 P4 gpio1 IO 3 usdhc1 VSELECT sdma1 EXT_E VENT 0 gpio1 IO 3 gpio1 IO 3 P118 N6 gpio1...

Page 48: ...41 F1 sai1 RX_DATA 5 sai6 TX_DATA 0 sai6 RX_DATA 0 sai1 RX_SYNC coresight TRACE 5 gpio4 IO 7 gpio4 IO 7 LVDS1_CH0_TX2_P 53 G2 sai1 RX_DATA 6 sai6 TX_SYNC sai6 RX_SYNC coresight TRACE 6 gpio4 IO 8 gpi...

Page 49: ...SS1_B gpio3 IO 2 gpio3 IO 2 gpio3 IO 2 76 G4 sai3 RX_SYNC gpt1 CAPTURE1 sai5 RX_SYNC gpio4 IO 28 gpio4 IO 28 gpio4 IO 28 68 F4 sai3 RX_BCLK gpt1 CAPTURE2 sai5 RX_BCLK gpio4 IO 29 gpio4 IO 29 gpio4 IO...

Page 50: ...l withstand an indefinite exposure to an applied VDD_IN that may vary over the 4 6V to 5 25V range without damage and it will operate over the entire VDD_IN range of 4 75V to 5 25V Ten pins are alloca...

Page 51: ...7W Play Audio VDD_IN 5V 0 7A 3 5W Ping Bluetooth VDD_IN 5V 0 7A 3 5W Ping Wi Fi VDD_IN 5V 0 86A 4 3W Ping Ethernet Eth0 and Eth1 VDD_IN 5V 0 85A 4 25W GPU Processor Graphics 3D Test VDD_IN 5V 0 96A 4...

Page 52: ...ctor is supported in i MX8M SMARC SOM operating temperature range is 25 C to 85 C 3 For more information on Thermal solution Heat sink refer the following section 3 2 2 Heat Sink For any highly integr...

Page 53: ...using RoHS compliant components and manufactured on lead free production process 3 2 4 Electrostatic Discharge iWave s i MX8M SMARC SOM is sensitive to electro static discharge and so high voltages ca...

Page 54: ...M SMARC SOM Top View The i MX8M SMARC SOM PCB thickness is 1 2mm 0 15mm top side maximum height component is 3 5mm Wi Fi Module followed by 3 5mm JTAG Header which is optional in default configuration...

Page 55: ...ndroid Industrial iW G33M SCMQ 4L002G E008G AIB With i MX8M Quad Core CPU 2GB LPDDR4 8GB eMMC and without WiFi BT Expansion Connector Android Industrial i MX8M QuadLite SMARC SOM iW G33M SCML 4L002G E...

Page 56: ...IA With i MX8M Dual Core CPU 1GB LPDDR4 8GB eMMC WiFi BT and no Expansion Connector Android Industrial iW G33M SCMD 4L001G E008G AIB With i MX8M Dual Core CPU 1GB LPDDR4 8GB eMMC and without WiFi BT E...

Page 57: ...ion of i MX8M CPU based SMARC SOM and its features Being a Nano ITX form factor with 120mm x 120mm size the carrier board is highly packed with all necessary interfaces on board connectors to validate...

Page 58: ...REL0 2 Page 58 of 58 i MX8 SMARC SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

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