MITS Janus Time Engine
Page 10 of 39
Copyright© Instrumentation Technology Systems 2020
20200929
1.1.9
Settings Flash
The following settings are saved to MJTE system flash such that each will survive a power cycle.
1.
Amplitude setting of IRIG B127 carrier output
2.
DHCP enabled/disabled state
3.
Network Time selection as NTP or PTP (slave)
4.
Output frequency of each clock (two)
5.
Polarity of 1PPS input edge alignment
6.
Polarity of both IRIG B00x inputs and outputs
7.
Polarity of Clock A, Clock B, 1PPS output edge alignment
8.
Preferred Time Reference
9.
Propagation delay offsets for IRIG and NTP inputs
10.
PTP terminal device or master clock setting
11.
Static IP Address, Port, Gateway, and subnet Mask
12.
Time Reference failover order
13.
Time Zone Offset
1.1.10
I/O Interface
There is a 40-pin interface header that provides signals to the and from the Photo-Sonics
Interface (PSI/O) PWA and the JTE Master Controller. Power for the JTE Master Controller, 12
VDC, comes from the PSI/O.
Differential IRIG B00x and 1PPS reference signals come from the PSI/O.
Controls and signals used to manage the PSI/O route through this interface.
This interface is NOT PC104 compliant and shall never be attached to a PC104 stack.
