ITE IT6506, Programming Manual

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IT6506 PROGRAMMING GUIDE
ITE Tech. INC. -2- 2013/11/12
•
Automatic loss of signal detection for Link management
•
Intelligent, programmable power management
•
144-pin LQFP (20mm x 20mm) package
Pin Diagram
17
18
19
20
21
22
23
24
25
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
26
27
28
29
30
31
32
33
34
35
62 63 64 65 66 67 68 69 70 71 72
IT6506
Displayport RX Chip
LQFP-144
(Top View)
I2S2
I2S0
D
C
A
U
X
N
D
C
A
U
X
P
R
X
3
N
R
X
3
P
R
X
2
N
R
X
2
P
A
V
C
C
A
G
N
D
R
X
1
N
R
X
1
P
A
V
C
C
R
X
0
N
R
X
0
P
D
V
D
D
1
8
P
G
N
D
P
V
C
C
A
S
P
G
N
D
A
S
P
V
C
C
R
X
A
U
X
P
R
X
A
U
X
N
X
T
A
L
IN
X
T
A
L
O
U
T
IN
T
#
P
C
A
D
R
I2S3
E
N
T
E
S
T
P
G
N
D
P
V
C
C
I2S1
WS
SCLK
E
M
E
M
_
V
P
P
P
C
S
C
L
P
C
S
D
A
QB2
QB3
QB6
QB7
QB8
QB9
QB5
QB4
IVSS
HPD
IVDD
IVDD
MCLK
SPDIF
OVDD
OVSS
OVDD
OVSS
QA20
QA21
QA26
QA27
QA28
IVDD
IVSS
QA30
QA31
OVDD
OVSS
QA22
QA23
QA24
QA25
QA32
QA35
D
V
S
S
1
8
D
V
D
D
1
8
A
G
N
D
A
V
C
C
D
V
S
S
1
8
QA33
QA34
36
QA29
S
Y
S
R
S
T
N
11
12
13
14
97
98
OVSS
QB10
QB11
QA16
QA17
QA18
QA19
95
OVDD
96
O
V
D
D
Q
B
2
1
Q
B
2
0
1
2
3
4
5
6
7
8
9
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120
101
102
103
104
105
106
107
108
119 118 117 116 115 114 113 112 111 110 109
QB14
QB15
QB16
QB17
QB18
QB19
DDCSDA
DDCSCL
IVDD
IVSS
V
S
Y
N
C
H
S
Y
N
C
IV
D
D
P
C
L
K
IV
S
S
D
E
Q
A
0
Q
A
1
Q
A
4
Q
A
5
O
V
D
D
O
V
S
S
Q
A
2
Q
A
3
Q
B
3
5
O
V
S
S
Q
B
2
6
Q
B
2
7
IV
D
D
IV
S
S
Q
B
2
8
Q
B
2
9
Q
B
3
0
Q
B
3
1
Q
B
3
2
Q
B
3
3
Q
B
3
4
O
V
S
S
Q
B
2
3
O
V
D
D
Q
B
2
2
QA8
QA9
QA10
QA11
QA12
QA13
QA14
QA15
IVDD
IVSS
99
100
Q
A
6
Q
A
7
10
15
16
IT6506 provides internal register accessed via PCSCL (pin 71) and PCSDA (pin 70) with slave
address 0xB0 where PCADR (pin68) is low, or 0xB2 where PCADR (pin68) is high under
100KHz speed.
The terms listed in the below table are using in future chapters:
Term Description Example
RegXX Where XX is a hexadecimal number, to indicate the
internal register accessed with subaddress XX of
I
2
C, and in bank 0.
Reg05 – access with I
2
C slave
address 0xB0/0xB2,
sub-address 0x05.