IT6506 PROGRAMMING GUIDE
ITE Tech. INC.
-25-
2013/11/12
LSVdRange
3
Main stream attribute data -Dynamic range
0: VESA range ( from 0 to the maximum )
1: CEA range
RO
LSVdPxlFormat
2:1 Main stream attribute data -Component format
00: RGB
01: YCbCr 4:2:2
10: YCbCr 4:4:4
11: Reserved
RO
LSCLKSync
0
Main stream attribute data -Synchronous clock
0: Link clock and stream clock asynchronous
1: Link clock and stream clock synchronous
RO
A8
Reserved
7:3 ------------------------------------------
RO
LSStereoVdAttr
2:1 Main stream attribute data -Stereo video attribute
00: No stereo video transported
01: for progressive vide, the next frame is RIGHT
eye, for interlaced video, TOP field is RIGHT eye
and BOTTOM field is LEFT eye
10: reserved and must not be used
11: for progressive video, the next frame is LEFT
eye, for interlaced video, TOP field is LEFT eye and
BOTTOM field is RIGHT eye
RO
LSVdIFrameEven
0
Main stream attribute data -Interlaced vertical total
even
0: number of lines per interlaced frame ( consisting
of two fields ) is an odd number
1: number of lines per interlaced frame ( consisting
of two fields ) is an even number
RO
A9
viditemcomp
7
Video format 5 attribute data compare bit-debug
RO
LSdiffVidFormat
6
Video main stream attribute data change
RO
LSHDCPSyncDet
5
HDCP SYNC DETECT
RO
LSAudMute
4
AudioMute_Flag
RO
LSNoVideo
3
NoVideoStream_Flag
RO
LSVdFrameMd
2
Interlace_Flag
RO
LSVdFieldTop
1
FieldID_Flag
RO
LSVBlank
0
VerticalBlanking_Flag
RO
B0
RegOtpCtrl
7:0 Otp encryption word selection for EMemory data
R/W
00101010
B1
RegOtpXor
7:0 Otp XOR value for EMemory data
R/W
10100101
B2
RegEMemWeakRd
7
EMemory weak read
R/W
1
RegEMemRWEn
6
EMemory Read/Write enable
R/W
1
RegMasterSel
5
EMemory control master selection.
0: HDCP circuit.
1: Register control. (RegB3[7:4]~RegB6)
R/W
0
RegROMBIST
4
ROM BIST enable
(BIST function is not implemented,
this bit is useless)
R/W
0
RegEnEMem
3
EMemory enable
R/W
1
RegPwrOnRdBksv
2
Automatically read Bksv when system power on
R/W
1
RegDisDecryp
1
HDCP decryption disable
R/W
0
RegCPDesired
0
HDCP enable
R/W
0
B3
RegDDCReq
7:4 Ememory DDC request command type.
0000: DDC request is valid.
Others: invalid.
R/W
0000
RegEMemLoad
3:0 EMemory load bit number.
This setting extends the write enable pulse width
for Ememory write.
Unit: 1T I2C CLK.
R/W
0010
B4
RegDDCHeader
7:0 Ememory DDC Header.
11100000: EMemory DDC Read Bank0.
11100010: EMemory DDC Read Bank1.
Others: invalid.
R/W
00000000
B5
RegDDCReqOffset
7:0 EMemory DDC Read Offset address.
R/W
00000000
B6
RegDDCReqByte
7:0 EMemory DDC request Byte Number.
R/W
00000000
B7
RegCRSymLockMax
7:0 Max number of locked symbol for Clock Recovery.
Note: Due to the double size of bus width, the
R/W
01000000
